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I have the following top level module:

module top #(
  parameter TOP_LEVEL_PARAM = 0
) (
  port declarations...
);

generate
  for (genvar i=0; i<2; i=i_1) begin: block
    if (TOP_LEVEL_PARAM == 0) begin
      do something....
    end else begin
      do something else...
    end
  end
endgenerate

endmodule

I can override this top level parameter in my simulation TB when I instantiate top by passing in a new value or by defparam, but how can I override it in other flows like synthesis, etc. which do not have any wrapper module around top?

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1
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This depends on the tools you are using. Usually it can be specified on the command line, but some tools will have it in their scripts. For example, Yosys has the chparam command.

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  • \$\begingroup\$ Thank you! I will check out specific tool's documentation. \$\endgroup\$ – Wilderness Feb 16 at 19:22
0
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Depends on tools. In Vivado: You can set a Synthesis property using TCL command

set_property generic {TOP_LEVEL_PARAM =1} [current_fileset]

In Modelsim: You can pass it while invoking vsim:

vsim -g/top/TOP_LEVEL_PARAM =1 top

For more about Vivado,refer Xilinx AR# 52217 and for Modelsim, refer vsim help

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  • \$\begingroup\$ Thank you! I will check out specific tool's documentation. \$\endgroup\$ – Wilderness Feb 16 at 19:22

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