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after reading those links :

Reverse-polarity protection P-channel MOSFET

Optimal method for multiple MOSFETs for LED driving with a shared power rail

Parallel MOSFETs

and this pdf :

International Rectifier - Application Note AN-941 - Paralleling Power MOSFETs

https://www.irf.com/technical-info/appnotes/an-941.pdf

i wanted to know if my design is right ? if it has any problems ?

max Current calculation : does max current will equal root ratio max power dissipation to max R on ,

without taking in consideration rise of temperature where it is positive coefficient , so if current increase temp increase leading to increasing Ron so current decreases leading to stability this also helps with parallel fet .

max current 2 fet combined will be just summation ?

capacitor sizing :

i want simple calculation of capacitance of capacitor where it will affect in rush current .

my design : enter image description here


update 2 :

enter image description here

so i added capacitor parallel to zener for inrush current

study caps values in reverse polarity case :

http://www.mediafire.com/file/ktecx6txuqk5pbn/capacitors_values_reverse_polarity_protection.xlsx/file

i can conclude from these that caps decreases the change of voltage , am i wrong?

what is p and f values analogue sim y axis means ?

to study in rush current : i have to make current probe right and cancel the current source in schematic ? because i tried this but change of current not appeared , should i make dc sweep voltage ?

is this method the way for studying in rush current ? :

https://electronics.stackexchange.com/a/352771/237957

i have read here

http://www.ti.com/lit/an/slva670a/slva670a.pdf

buck converters make u dont need in rush current limiter because they have soft start functionality

just wanna make sure that buck converters will do the work ?

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  • \$\begingroup\$ If you are trying to design a reverse voltage protection device that also controls in rush current then your schematic is flawed. Also the IR document about paralleling MOSFETs is missing a key ingredient when paralleling MOSFETs used for linear control (in rush protection). \$\endgroup\$ – Andy aka Feb 15 at 17:54
  • \$\begingroup\$ See this q and a for details: electronics.stackexchange.com/questions/472375/… and also this: electronics.stackexchange.com/questions/361407/… \$\endgroup\$ – Andy aka Feb 15 at 18:04
  • \$\begingroup\$ @Andy aka thanks for your reply i really was amazed by thermal runaway of mosfet . But i didn't understand about the in rush protection ,aslo it would be grateful if u helped me calculating capacitance of capacitor . \$\endgroup\$ – Ahmed elmenshawie Feb 15 at 18:54
  • \$\begingroup\$ The capacitor needs to be across the zener diode. Why don’t you simulate the effect? \$\endgroup\$ – Andy aka Feb 15 at 19:48
  • \$\begingroup\$ @Andy aka thanks for your useful reply , sure i will do simulation im just far from my pc now . I have read herehttps://electronics.stackexchange.com/questions/106764/pmos-inrush-current-limit-where-to-place-capacitor \$\endgroup\$ – Ahmed elmenshawie Feb 15 at 19:54
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Modified to better suit what the OP probably requires

i want simple calculation of capacitance of capacitor where it will affect in rush current

Firstly and importantly, the capacitor on each MOSFET needs to be in parallel with the zener in order to achieve inrush current limiting but, the confusion here surrounds both MOSFETs being in parallel. They are actually positioned to be reverse polarity protection devices and cannot be used as inrush limiters (contrary to what I originally understood and wrote so, sorry about this).

So, instead, think about the reverse polarity circuit (without a gate capacitor) then, after that MOSFET circuit, think about using another P channel MOSFET with its source after the reverse polarity MOSFET's source: -

enter image description here

So, assuming you do this, the rest of my answer is relevant....

You need to think about the CR time of the capacitor and resistor to ground. Quite literally C x R is the time constant and for this type of circuit, the MOSFET might be regarded as being fully conducting at about 50 % of CR. This assumes that the MOSFET fully conducts at about 12 volts between gate and source.

Given that your supply is 48 volts, at the end of the first CR time period you’ll get about 24 volts across the capacitor, it isn’t too far wrong to estimate that at 50% of CR, the voltage will be 12 volts.

However, a lot of MOSFETs might be pretty well conducting at 3 volts so, there’s a fair degree of slop in this gearbox. That’s why I recommend simulating and messing around with values etc..

As for paralleling MOSFETs, it’s not clear cut by any means when operating them linearly through the dangerous zone so play safe and choose MOSFETs that are intended for linear operation. The main clue is page 1 of the data sheet. If it says typical applications are switching circuits or converters then make absolutely sure you give enough headroom. Alternatively go to a company called IXYS and pick the appropriate range designed for linear applications.

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  • \$\begingroup\$ Comments are not for extended discussion; this conversation has been moved to chat. Any conclusions reached should be edited back into the question and/or any answer(s). \$\endgroup\$ – Dave Tweed Feb 18 at 0:00

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