I know that if a MCU pin is configured as "input" and it is not connected to any pull up/ pull down resistor, it is said to be floating. In this situation, we could say that the pin is in series with the (very) high input impedance of the MCU, which is eventually connected to ground. So we could say that the pin is in a (very) weak pull-down condition, with the MCU input impedance acting as the (very high) pull-down resistor. So basing on this assumptions, if we suppose that no significant interference acts on the pin, I would say that (if we wait long enough) the pin voltage will be eventually "pulled to ground". Where am I going wrong?
Have recently been characterizing an input pin on a PIC microcontroller. The pin can be alternately set to CMOS in/out, Schmitt input, or analog input. When set for Schmitt input:
- Data sheet specification of leakage current is +/- 5 nA.
- Measured leakage current at room temperature is less than 3 pA.
Similar results were measured years ago on a different PIC microcontroller. Be aware that leakage current is very temperature-dependent, and can be in either direction. So you cannot assume that it floats to a logic low state.
It is possible that electric field of a hand-waving over a floating pin can change its logic state.
A CMOS chip's input circuit generally includes both P channel and N channel transistors. If the chip is powered, then the (tiny) gate leakage currents can be in either (or both) directions: to ground, or to some internal voltage rail(s). The process variation may not allow one to pre-determine which direction of leakage is greater (unless the chip was designed with specific direction and process+operating margin).
tl; dr version: The input impedance of a CMOS input is high, practically an open circuit. It needs to be terminated, either by tying to a supply or by driving it with a signal. It cannot be left floating.
A CMOS input is a capacitance: the gate-source capacitance on the input pair. Your intuition tells you that even though it is a capacitance, the charge on the input should bleed off somehow over time. In fact CMOS gates do that: they have a small Vgs leakage. There is also leakage in the input protection circuit - a pair of reverse-biased diodes that catch voltage above VDD and below Vss.
However, there's two confounding things going on. First, the two FETs (P and N) have their sources tied to the Vdd and VSS rails, respectively (as do the protection diodes.) So their leak paths are to opposite rails: P FET to Vdd, N FET to Vss.
If the leakages were equal, then in theory the input would find a bias point in between. In reality this is very hard to predict because gate leakage varies wildly with process and temperature. It cannot be counted on as a bias.
Second, this Vgs gate leakage is very, very small, and so is the gate capacitance (a few pF typically.) On the other hand, the influence of outside electric fields can easily couple onto the floating pin and cause it to change state. This is in fact how a basic capacitive touch sensor works: hum pickup from the body.
Bottom line: never leave a CMOS input floating. Always tie it off.
In this situation, we could say that the pin is in series with the (very) high input impedance of the MCU, which is eventually connected to ground.
Where am I going wrong?
You are going wrong in forgetting it is also eventually connected to Vdd, not just GND. So why would it eventually pull to GND over Vdd?
Where am I going wrong?
...to the fact that a pin can be connected to two CMOS in push-pull configuration, and they could leak current in an unpredictable way...
Thinking better, even if the pin is a pure CMOS input, you can not know in advance what will happen. May be that for a short time our CMOS input behaves like a load.
A (non-CMOS) transistor can be very different, but if you restrict the question to MCUs, I believe it is difficult to find normal transistors.