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I want to make an MSP430G2553 communicate using SPI with a 7-segment display and with another microcontroller MSP430G2452.

So the MSP430G2553 would be the master and both the 7-segment display and MSP430G2452 would be slaves. The master will acquire a measurement from the slave microcontroller MSP430G2452 and then display it on the 7-segment display once per second.

I have been led to believe that it is not possible to connect the two slaves on the same SPI bus. Is this the case and if so why not?

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    \$\begingroup\$ to share a spi bus you need to chip selects, use other gpio pins as the chip selects and manually control them. should be able to have a few slaves before you run out of pins \$\endgroup\$ – old_timer Feb 16 at 16:38
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A number of SPI slaves can be connected in one of two configurations:

Single Slave-Select daisy-chained

enter image description here

Here the entire SPI bus is treated as one big shift register and the master must know the order of devices in the bus chain and their respective register widths. It is also necessary to write all devices at the same time in the same bus transaction. Often the /SS line in this case is controlled by the SPI peripheral controller.

Independent Slave-Selects - wire-OR'ed MISO/MOSI

enter image description here

Here each device can be selected and written to independently at any time. Normally the /SSn lines are under software control and the master can select and access each device at any frequency and in any order.

The first configuration requires that each slave has a MISO. Some "write-only" devices such as 7 segment displays lack an MISO so can only share an SPI wired as in the second case, where such devices will not be connected to MISO.

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  • \$\begingroup\$ Notably, in case of a "dumb" display device in a daisy-chain with a "smart" duplex MCU slave, the display should be placed first in the daisy chain, so that new data to the display is clocked in from the master. Otherwise, the slave's data for the master would end up passing through the display, which could lead to unintended side-effects. \$\endgroup\$ – Lundin Feb 17 at 9:43
  • \$\begingroup\$ @Lundin I redrew the diagrams to replace the ones I clipped from Wikipedia. The daisy-chain one appears to be an old version (two slave 1), according to the edit log I managed to replace the correct one with an earlier incorrect one. It was very late. Thanks for spotting that - appreciated. \$\endgroup\$ – Clifford Feb 17 at 11:07
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It is possible to connect two and more slaves to an SPI bus, in a common setup there is only one master in an SPI bus however there is also the possibility for an SPI bus with multiple masters.

For using the MSP430G2452 as SPI slave you have to configure it in slave mode.

This is on page 400 in the users manual (http://www.ti.com/lit/ug/slau144j/slau144j.pdf) :

14.2.3.2 SPI Slave Mode

The USI module is configured as SPI slave by clearing the USIMST and the USII2C bits. In this mode, when USIPE5=1 SCLK is automatically configured as an input and the USI receives the clock externally from the master.

Then use the common Slave Select (SS) lines (also named as Chip Select, Slave Transmit Enable, Chip Enabler) to connect multiple slaves to the SPI bus, whichs master is the MSP430G2553

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  • \$\begingroup\$ In the example that I'm triying to implement, it is required to justify why is not possible to put the MPSP430G2452 on the same SPI bus with the 7-segment display and consider it as a second slave. I didn't find a reason. could it be a synchronisation problem? each measurement from the MSP430G2452 should be displayed each one second? means the master will read from MSP430G2452 and display on the 7-segment display each 1 s. \$\endgroup\$ – Didon Feb 16 at 13:49
  • \$\begingroup\$ Where is this example ? \$\endgroup\$ – ralf htp Feb 16 at 13:52
  • \$\begingroup\$ It is a homework..it is not on the net. Last question please, could it be due to 3 wire SPI mode and 4wire SPI mode? \$\endgroup\$ – Didon Feb 16 at 14:39
  • \$\begingroup\$ 3-wire SPI is half-duplex (totalphase.com/support/articles/…) but you are right, 3-wire SPI has a SS and so i still can see no reason why there should not be 2 slaves on an SPI bus \$\endgroup\$ – ralf htp Feb 16 at 17:47
  • \$\begingroup\$ Yes i also think this ... \$\endgroup\$ – ralf htp Feb 16 at 17:50

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