I'm routing traces between a microcontroller and a TFT display (24-bit RGB, clock frequency at 18 MHz).The stackup is:
- L1 - Signal
- L2 - GND (solid layer)
- L3 - PWR (solid 3.3V in the region of interest)
- L4 - Signal
Components are only on top in order to reduce manufacturing cost (it also explains the choice of a 4-layer stackup).
I designed a first version of this board which worked fine and allowed to develop and test all the software. Now, I'm currently designing a new board version which some mechanical constraints. Some signals were a bit noisy but display worked fine. I would like to improve the routing a bit.
I see two different strategies to route the signals between the MCU and the display. I guess it is understandable that I cannot route only on the top layer even though it would be ideal... The screenshots below are only first drafts and not layout for production.
Option 1 : that is the option I used in the first boards, vias are both on the MCU side and on the connector side (just before the network of 0 ohm resistors)
Option 2 : vias are concentrated around the MCU.The goal was to have the return current path goes through the MCU decoupling capacitors to jump from the 3.3V plane to the ground plane.
- Is any of these options better from the point of view of signal integrity/EMC?
- Option 2 makes me want to have a ground area within the power plane (L3) and vias between L2 (ground plane) and L3(ground area within power plane), so the return current path can freely jump from L3 to L2 and the other way around (see picture below) Is it something which would make sense? I've never seen such a design choice in other PCB layouts but I didn't see people routing TFT display on L4 PCB either.
- Is there a better way to solve it?
EDIT 1: Even though the question is not about length matching, I give the numbers here to justify why I didn't do any length tuning.
Clock frequency < 18 MHz <=> Period > 55 ns
For a signal speed in PCB is 15 cm/ns and an allowable skew of a quarter of the period, it gives 2 meters. I believe the mismatch of 3 cm in the examples above is not important.
EDIT 2: Quick measurement of a data line (purple) and a clock line (yellow) on the current board with a screen connected and running (it is not a proper 10/90% measurement). I don't really trust these numbers because it is a 100 MHz scope with a 100 MHz probe (20 pF probe). However, it seems to fullfil the 12 ns setup and hold time requested for the screen. Drive strength on the MCU is at the lowest settings (it divides the rising time by two at the highest setting but it introduces some ringing as much as the scope can tell).
This figure is from the first revision of the board with a layout close to option 1 but with signal lengths 3 cm shorter and a mismatch between lines of 3 cm. Screenshot below.