Question about IDELAYE3 of Xilinx FPGA

Question

I'm using xilinx FPGA(xcku025-ffva-1156) . I want to use the xapp1315  in my design for 1:7 deserialization.

In Xapp1315 design file, an external clock is used to enter the fpga through IBUFGDS.

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But in my design, there are many other logics, so xapp1315 design can not be top file.

The main problem is that I have only 50MHz external input clock port, but this xapp 1315 design doesn't support this frequency.

The solution I thought was as follows.

Since the input of IDELAYE3 was no longer coming from the IO buffer, I used a DATAIN port instead of the IDATAIN port.

(I also changed the delay_src from IDATAIN to DATAIN).

However , the simulation results are different from the original xapp1315 design.

The rx_ready signal is not asserted. The output seems as if it continues to bitslip.

Is the way I thought it was wrong?

Is it a problem to create a differential clock in mmcm or is it a problem or is IDELAYE3 misused?

Or Is there any good method to make 100Mhz external input clk port by using 50Mhz external input clk?

Thank you for reading me the long question.

Answer 1

That clock input is supposed to be synchronous with the LVDS data, so inserting a PLL like that does not make any sense. Not to mention it's not possible as drawn as the IBUFDS_DIFF_OUT instance is an input buffer and as such may only be connected directly to the appropriate IO pins on the FPGA. This is because those instances are physically located in the FPGA IO banks, it is not possible to configure them to be connected to anything else than the physical package pins.

If clock frequency you're interested in is outside the capabilities of that app note, then you're going to have to make more extensive modifications. That is, of course, assuming the example design actually does what you want it to do, which isn't clear. TBH, this sounds like an X-Y problem. What are you really trying to accomplish here?