I', using xilinx ultrascale FPGA (xcku025-ffva-1-a)

I am referring to application notes provided by xilinx.

I am going to use the reference code provided in xapp1315.

In this reference code, an external clock of 100 MHz enters to FPGA, passes IBUFDS_DIFF_OUT, and then goes to idelaye3. enter image description here

I am going to design my top file containing this logic as shown in the picture below

The reference code should receive 100 MHZ external clocks (go to IBUFDS), but my top design has only 50 MHZ external clocks.

enter image description here

What's the best way to solve a case like this?

  • \$\begingroup\$ Modify the reference code? \$\endgroup\$ Feb 17, 2020 at 12:57
  • 1
    \$\begingroup\$ Does this answer your question? Question about IDELAYE3 of Xilinx FPGA \$\endgroup\$ Feb 17, 2020 at 13:03
  • 1
    \$\begingroup\$ You have already asked this question. If you have more information, edit the existing question instead of opening a duplicate. \$\endgroup\$ Feb 17, 2020 at 13:03
  • \$\begingroup\$ oh. sorry, I didn't know there was an answer to the previous one, so I posted a new question and forgot to delete the previous one. \$\endgroup\$ Feb 17, 2020 at 23:12

1 Answer 1


This is not possible as you have drawn your block diagram; the IBUFDS_DIFF_OUT is an input buffer and as such it may only be connected directly to the proper IO pins; it cannot be driven from within the FPGA. What you need to do is edit the reference design to use a 50 MHz input clock. This could be as simple as changing the settings of an existing MMCM or PLL. Or maybe you need to add an MMCM or PLL instance.


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