I', using xilinx ultrascale FPGA (xcku025-ffva-1-a)
I am referring to application notes provided by xilinx.
I am going to use the reference code provided in xapp1315.
I am going to design my top file containing this logic as shown in the picture below
The reference code should receive 100 MHZ external clocks (go to IBUFDS), but my top design has only 50 MHZ external clocks.
What's the best way to solve a case like this?