Is this a good design for a 0...7 counter?

My daughter's electronics teacher recommends to realize a counter from 0...7 as follows:

It shall give an output pulse (for a subsequent circuit) when the button is hit the 8-th time. For me this doesn't give sense: when the Outputs are 1-1 and I hit the button a fourth time, there is a race condition within the and-gates and the output of the flip flops. In my simulation it resets (see the async reset inputs) when I press button the 4th time.

Of course, it depends whether which change of the yellow marked nodes is faster...

Maybe it works by accident - but isn't this extremely bad design?

I would solve it like:

• If you are using a button without a debounce circuit then both designs are bad. Feb 17, 2020 at 13:44
• Of course the buttons are debounced. Otherwise it wouldn't give sense at all. This is an example on educational level - not a real life problem Feb 17, 2020 at 14:07

Maybe it works by accident - but isn't this extremely bad design?

Yes, it is. But your proposed solution is only half better.

First, you are correct about a race condition at the 3 to 4 transition. Whether the reset pulse produced will work in a real setup is anybody's guess. It depends on whether or not the required reset pulse width is greater than the propagation delay of an AND gate.

For instance, a 74HC73 FF https://assets.nexperia.com/documents/data-sheet/74HC_HCT109.pdf has a minimum reset pulse width at 5 volts of 16 nsec (min) to 5 nsec (typ). A 74HC08 AND gate https://assets.nexperia.com/documents/data-sheet/74HC_HCT08.pdf has a typical propagation delay of 9 nsec and a max of 18 nsec. So a slow AND gate will reliably reset typical FFs in this model, but a fast AND gate will not reset a slow FF. Since the actual reset performance of any individual FF will vary, it's entirely possible that some FFs will reset, some won't, and some will do so randomly.

Note that this analysis isn't actually correct - by the time the 7400 series had progressed to making flip-flops, the use of active-low resets had been adopted, which would use a NAND gate for the second gate rather than an AND. But I hope you get the point.

Your reset pulse will only be as wide as one propagation delay of an AND gate plus the propagation from reset to output of a flip-flop - and this varies from unit to unit. If your last FF is particularly fast and the others particularly slow, you may well get unreliable reset.

Just as a general rule, if you're going to use synchronous counters, as is done here, NEVER use asynchronous controls such as resets. Except for global events like power-on resets, subsystem resets, or things of that nature.

In this respect, your proposed improvement will be worse than the original, because the reset pulse will be narrower.

However, you're on the right track. Sort of.

As henros points out, for a 0 - 7 counter, you don't need any reset at all. Binary 8 is simply a 1 in the 4th bit, with the 3 lsbs 0. If you start at zero, the eighth clock pulse will automatically set the first three back to zero. So you can simply use the 4th FF to generate the output pulse (although I'd really recommend adding some delay from the output to the reset, and let the first 3 run freely.

However, in a real system you would use the clear inputs as an overall reset. Otherwise there is no way to guarantee that the system would start with all the FFs at a zero output.

As shown: b,c or d does the job without any gates, and d is fully synchronous! (Taken from "Gateless Scalers with J-K Flipflops", P A Neetson, Philips Eindhoven, 1968) BUT you do need a bounceless clock.

• A 0..7 counter is a basic 3-bit counter with 8 states - the OP isn't looking for a 7-state counter. Feb 17, 2020 at 14:25
• The counter shall reset to 0-0-0 when it is clocked 8 times. So it starts with 0-0-0 (idle), goes up to 1-1-1 and finally shall reset on another clock input, thereby emitting a "clock spike" on its output. What I have resets after 4 input clock events, but the behavior is somehow undefined. Feb 17, 2020 at 15:24
• Three of these circuits produce a single negative-going output after seven clock cycles - which is exactly what was originally specified. Intermediate states of the device were not defined. Feb 17, 2020 at 16:23
• If I have misinterpreted the requirement, then use three synchronous JK's connected as a binary counter and use the negative-going edge from the third as the output - either way, it avoids gate delays. Feb 17, 2020 at 16:47