I've decided to build a a PLL based synthesiser to produce the Local Oscillator(LO) signal for my DIY transceiver. My aim is to try to use commonly available (preferably inexpensive) parts in what is a mainly educational exercise.
I'm a total newcomer to the world of frequency synthesis and PLLs, but what I've read so far suggests I'm looking at a multi-loop configuration (two in this case) to achieve a step size suitable for SSB (around 10Hz) with a fast lock time.
This question is centered on the course tuning loop with a VCO output frequency of 34.5 MHz to 36 MHz (the VCO is a standard double varactor tuned Hartley). The reference frequency will be 125 KHz (produced from a 4 MHz crystal divided down by 2^5 using a 4060) and the phase detector will be the venerable 4046.
The output frequency is a challenge as it's tantalizingly just out of range of many commonly available divider ICs (the oft quoted 4059 is one example, but its maximum clock is around 30 MHz). I figured this might be an issue, so I ordered some difficult (but not impossible) to find MB501L dual-modulus prescaler ICs (which have a useful 10MHz lower limit).
I figure I'll need to divide my 34.5MHz output by 276 to get a 125KHz signal for the phase compare, so that's N=4 and A=20, which I'll handle using a microprocessor (the 530KHz odd divided down signal should pose no issues). I've glossed over a lot of detail here, but the design of the loop itself isn't really the issue.
What I'd really like to know is, are there any commonly available alternatives to dividing down the 34/36 MHz signal? I know I could simply use a cheap si5351 module and be done with it, but I'm doing this for educational reasons, so I'd like to crawl a little first before I sprint!
