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I've decided to build a a PLL based synthesiser to produce the Local Oscillator(LO) signal for my DIY transceiver. My aim is to try to use commonly available (preferably inexpensive) parts in what is a mainly educational exercise.

I'm a total newcomer to the world of frequency synthesis and PLLs, but what I've read so far suggests I'm looking at a multi-loop configuration (two in this case) to achieve a step size suitable for SSB (around 10Hz) with a fast lock time.

This question is centered on the course tuning loop with a VCO output frequency of 34.5 MHz to 36 MHz (the VCO is a standard double varactor tuned Hartley). The reference frequency will be 125 KHz (produced from a 4 MHz crystal divided down by 2^5 using a 4060) and the phase detector will be the venerable 4046.

The output frequency is a challenge as it's tantalizingly just out of range of many commonly available divider ICs (the oft quoted 4059 is one example, but its maximum clock is around 30 MHz). I figured this might be an issue, so I ordered some difficult (but not impossible) to find MB501L dual-modulus prescaler ICs (which have a useful 10MHz lower limit).

I figure I'll need to divide my 34.5MHz output by 276 to get a 125KHz signal for the phase compare, so that's N=4 and A=20, which I'll handle using a microprocessor (the 530KHz odd divided down signal should pose no issues). I've glossed over a lot of detail here, but the design of the loop itself isn't really the issue.

What I'd really like to know is, are there any commonly available alternatives to dividing down the 34/36 MHz signal? I know I could simply use a cheap si5351 module and be done with it, but I'm doing this for educational reasons, so I'd like to crawl a little first before I sprint!

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  • \$\begingroup\$ You could use a mixer to bring the 34/36 MHz signal into a more manageable range. \$\endgroup\$
    – Peter Smith
    Feb 17, 2020 at 16:39
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    \$\begingroup\$ Have used a PIC microcontroller as the counter/divider. Its 8-bit TMR0 has an asynchronous prescaler that can accept a 34.5MHz square wave. An additional NAND chip is needed to read the prescaler value (since the PIC itself can't read that particular register). The PIC clock is crystal-controlled, acting as an accurate frequency reference. \$\endgroup\$
    – glen_geek
    Feb 17, 2020 at 16:51
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    \$\begingroup\$ Most modern FPGAs should be able to handle 36MHz; they are available as demonstrator / evaluation kits at a modest price in many cases. See for example allaboutcircuits.com/news/… \$\endgroup\$
    – Peter Smith
    Feb 17, 2020 at 16:52
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    \$\begingroup\$ ADF4110 springs to mind. It needs an oscillator frequency of above 80 MHz but has got the division ratios you appear to require and easily converses with a PIC. \$\endgroup\$
    – Andy aka
    Feb 17, 2020 at 17:10
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    \$\begingroup\$ The Lattice ICE (is that the right name?) FPGAs are small, low power, cheap, and well supported. \$\endgroup\$
    – TimWescott
    Feb 17, 2020 at 18:00

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ADF4110 springs to mind. It needs an oscillator frequency of above 80 MHz but has got the division ratios you appear to require and easily converses with a PIC.

So, how do I get my target frequency in this case? I'm guessing I'll need an additional mixer to down-convert, am I right? Otherwise, this IC looks great.

Just make an oscillator that runs at circa 100 MHz or use the ADF4002. Common collector colpitts is usually easier than Hartley: -

enter image description here

@Andy aka ADF4002 seems like the way to go (and it's cheaper too!) Thanks again, as usual.

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