I am studying this circuit, but unable to understand why they put capacitor C30, C33, EC4, inductor L3 on their current place, and their value, i keep searching on google for decoupling capacitor, sound like related, but still can not understand
L3 and C33
Further to the above answers note that your schematic shows an inductance of 10uH which is almost certainly wrong. As others have commented, L3 should be a ferrite bead. These are described by their impedance at a certain frequency and not their inductance.
Typically they have near zero resistance to DC current but high impedance at the frequency of choice. The datasheet doesn't provide a recommendation, but the circuit will likely function with a zero ohm resistor here if you aren't trying to pass RF emissions tests. If you want to fit a ferrite then it should have maximum impedance at 10MHz I would guess (to limit the transfer of the Ethernet signal back into 3.3v rail).
C33 is doing the opposite. It blocks DC current from flowing into ground but allows AC to pass. The higher the frequency the lower the impedance. There isn't a great way to choose C33 value but the datasheet suggests 0.1uF. At 10MHz I would want this to be less than the ferrite impedance by at least a factor of 10, which should be easily achievable.
The ENC28J60 PHY works in current mode by pulling current through the center tap into the two tpout Pins. By pulling more into one than the other it creates a differential voltage. The average current is 40mA typically.
Your ferrite has to pass that current, hence the 80mA recommended rating for the ferrite.
Some other PHY designs operate in voltage mode and these have different requirements to interface to the magnetics. The circuits are not interchangeable! Be careful when googling!
There is a voltage regulator in the chip. It produces the 2.5V required by the analog sections of the PHY.
The 10uF is a filter capacitor that stabilises the control loop of the regulator. The control loop is the circuit that varies the resistance of the regulator's pass transistor to try to keep the output at 2.5v. When the voltage drops the loop reduces the resistance to boost it and vice versa. In steady state the resistance is unchanging. When the load is varying quickly (typically during transmit) the control loop will try to react but won't be able to keep up. If the transients arrive too quickly the loop can become unstable and start to oscillate such that the output voltage chops between a higher and lower voltage quickly.
That's where EC4 comes into play. It filters out fast transients in the load and 'hides' them from the control loop. The chip designers recommend a minimum of 1uF and ideally 10uF. Note that the ESR is as important to the loop stability as the capacitance. So a low ESR 1uF could easily perform better in this circuit than a high ESR 10uF.
Probably you should use an electrolytic as suggested by the datasheet even though ceramic caps are available in 10uF. That's because ceramic caps have ultra low ESR and sometimes the control loop is only stable with some ESR ... Nothing is ever easy!
This is performing a similar function to EC4 but in this configuration these are referred to as decouplers or bypass caps.
The purpose is simply to bypass the inductance of the supply rails.
If you had a perfect supply with zero inductance between the 3.3 regulator and the VDD pin and also back the other way through the VSS pin and the regulator ground pin then you would not need the bypass cap.
The reality is that this is not possible.
When the chip uses current it does so in quick pulses as various gates and outputs switch.
The inductance in the supply rails resists these pulses and so the voltage across VDD/VSS swings up and down.
In extreme cases this swing can cause the chip to operate unreliably due to over or under voltage.
The bypass cap eliminates the swing. When the chip increases current usage, the cap drains to supply that current while the inductance in the supply rail is resisting the change in current. Similarly when the chip decreases current usage the bypass charges up, absorbing the current that continues to flow while the inductance in the rail responds to the reduced load.
One could go to a lot of effort to calculate the required bypass based on PCB design, chip current consumption patterns, etc. In reality we use what's in the datasheet.
In this case that is 0.1uF ceramic for all supply/ground pairs. Don't be tempted to change those values without good cause. Bigger isn't better.
Your example is an ethernet interface, in which the connection to the magnetics isn't directly shown. But the input TPIN pair and the output TPOUT pair are connected to transformers (the "ethernet magnetics") which send or receive pulses down the twisted pair cable to the other ethernet devices.
ENC28J60 Datasheet (italic references are to the datasheet)
In practice, especially for a circuit like this, most designers will follow the datasheet's sample circuit pretty closely:
Your C30 is a decoupling capacitor, for keeping the power supply clean. There are actually five VDD and VSS pairs on this chip, for the various subsystems, and the datasheet recommends an 0.1μF ceramic capacitor per pair (section 2.4). Think of these as immediately local reservoirs of power for when the chip has very small, very short, increases in power demand -- ie, every time it changes any signal. See this answer for more on these.
Your EC4 is part of an internal 2.5V regulator (section 2.4), and is off-chip because it's a relatively large value: Typical 10μF, min 1μF, (table 1.1). The ethernet signal is made by driving 2.5V out of TPOUT+ and TPOUT-, and differentially changing the current sunk. This creates spikes which go through the top transformer of the reference diagram. Think of it as the tank from which the ethernet signals are sent. See this answer about how a regulator input capacitor works.
Your L3 and C33 are for EMI reduction, as shown on the Termination and External Connections diagram of the datasheet. They help keep interference down by making a low-pass filter that absorbs radio frequencies. L3 is a ferrite bead, which has high resistance. I can tell you from experience the circuit will function perfectly well without these, but I didn't measure the noise. Remember that the TPOUT pair can be connected (through the ethernet magnetics) to a pretty long wire which can function as an effective antenna. Lots of countries (but notably the United States where ethernet was designed) have legislation against emitting excessive interference.
Observations: your sample circuit appears to omit some of the decoupling capacitors (unless they are on a different portion of the diagram); quite reasonably it uses E24 resistor values 51R and 2K4 instead of 49R9 and 2K32; for unknown reason, perhaps cost or board space, it using 0.01μF where datasheet recommends 0.1μF.
Because the datasheet says so on page 7.
For C30, in the text on page 7 on the right you'll find:
Each VDD and VSS pin pair should have a 0.1uF ceramic bypass capacitor (not shown in the schematic)
For C33 and L3, A look in the schematic tell us it's purpose shown with additional remarks:
(Note that L3 is not an inductor, but a ferite bead!)
These components are installed for EMI reduction purposes.
Ferrite Bead should be rated for at least 80 mA.
For EC4, the datasheet specifies a 10uF cap in the schematic, but I a larger one will also work. Possibly better in noisy environments.