0
\$\begingroup\$

I'm very new to VHDL, please excuse my question. My output values are always U. I cannot figure out why.

This is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity first is
    Port ( R : in STD_LOGIC;
           F : in STD_LOGIC;
           W : in STD_LOGIC;
           WI : out STD_LOGIC;
           CF : out STD_LOGIC);
end first;

architecture Behavioral of first is

begin

WI <= not (R and W);
CF <= F and F;
end Behavioral;

And this is my test bench:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity testBench1 is
end testBench1;

architecture Behavioral of testBench1 is
COMPONENT test1
 PORT( F : IN STD_LOGIC;
 R : IN STD_LOGIC;
 W : IN STD_LOGIC;
 CF : OUT STD_LOGIC;
 WI : OUT STD_LOGIC);

 END COMPONENT;
 SIGNAL F : STD_LOGIC;
 SIGNAL R : STD_LOGIC;
 SIGNAL W : STD_LOGIC;
 SIGNAL CF : STD_LOGIC;
 SIGNAL WI : STD_LOGIC;
BEGIN
 UUT: test1 PORT MAP(
    F => F,
    R => R,
    W => W,
    CF => CF,
    WI => WI
 );
 testBench1 : PROCESS
 BEGIN
 wait for 100 ns;
 R<='0';
 W<='0';
 F<='0';

 wait for 100 ns;
 R<='0';
 W<='0';
 F<='1';

 wait for 100 ns;
 R<='0';
 W<='1';
 F<='0';

 wait for 100 ns;
 R<='0';
 W<='1';
 F<='1';

 wait for 100 ns;
 R<='1';
 W<='0';
 F<='0';

 wait for 100 ns;
 R<='1';
 W<='0';
 F<='1';

 wait for 100 ns;
 R<='1';
 W<='1';
 F<='0';

 wait for 100 ns;
 R<='1';
 W<='1';
 F<='1';


 END PROCESS;
end Behavioral;

I appreciate any help, I just cannot find a solution. Thank you all.

\$\endgroup\$
2
  • 1
    \$\begingroup\$ How have you bound component test1 to entity first? Or have you left it unbound in the testbench? \$\endgroup\$ Feb 18, 2020 at 21:39
  • 2
    \$\begingroup\$ There doesn't appear to be a test1 in library work. UUT isn't bound during elaboration. That can be cured with an explicit binding indication in a configuration specification after the component declaration in the testbench or rationalizing the component name and entity name (first). Note the port order doesn't match, also requiring named association in the UUT port map. The configuration specification could be for uut: test1 use entity work.first; . \$\endgroup\$
    – user8352
    Feb 19, 2020 at 0:03

1 Answer 1

1
\$\begingroup\$

Your testbench component/UUT is named incorrectly.

You're module is named "first", but your testbench is declaring a component "test1". So your testbench is trying to run tests on a component that doesn't exist. Rename all instances of "test1" in your testbench to "first" and it should work.

COMPONENT first
 PORT( 
 F : IN STD_LOGIC;
 R : IN STD_LOGIC;
 W : IN STD_LOGIC;
 CF : OUT STD_LOGIC;
 WI : OUT STD_LOGIC
 );
 END COMPONENT;

and

 UUT: first 
 PORT MAP(
    F => F,
    R => R,
    W => W,
    CF => CF,
    WI => WI
 );

As an aside, all of your naming conventions are painfully obfuscated. Name things in a manner that you can understand what they are without context. Avoid names like "first", and "test1", also avoid single character or hyper-abreviated port/signal names like 'F' and 'WI', unless it's solely a D flip-flop where D, Q, and CLK, are standard nomenclature.

ALSO ALSO, in your module you're assigning CF <= F and F; this is identical to just doing CF <= F;. ANDing a value to itself will always just output itself.

\begin{array}{|c|c||c|} F & F & CF \\ \hline 0&0&0&F = 0\\ 0&1&0&will\ never\ happen\\ 1&0&0&will\ never\ happen\\ 1&1&1&F = 1\\ \end{array}

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.