Designing FSM using Verilog

Question

The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.

My Code

module top_module(
input clk,
input in,
input areset,
output out); //
reg state,next_state;
parameter A=2'b00,B=2'b01,C=2'b10,D=2'b11;

 always @(*)
    begin
         case(state)
                2'b00: next_state= in ? B : A;
                2'b01: next_state= in ? B : C;
                2'b10: next_state= in ? D : A;
                2'b11: next_state= in ? B : C;
            endcase
    end
always @(posedge clk ,posedge areset)
    begin
        if(areset)
            state<= A;
        else
            state<= next_state;
    end

assign out= (state==D);
endmodule

It is showing 29 mismatches. Please tell me where did i go wrong. The images of output is as shown

Answer 1

You really need to include an actual link to the website in question — I finally found it here.

Did you read any of the warning messages that the site spits out about your code? They make the problem rather obvious. For example:

Warning (10199): Verilog HDL Case Statement warning at top_module.v(15): case item expression never matches the case expression File: /var/www/verilog/work/vlgNC2KRa_dir/top_module.v Line: 15

This case can never occur. One common bug is that you declared the wrong size for a signal (Also look for warnings about truncating values). For example, case(a[0]) 2'b11: something; endcase never matches because a one-bit signal can never be 2'b11.

Fixing that one problem allows your code to pass all tests.