The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.

enter image description here

My Code

module top_module(
input clk,
input in,
input areset,
output out); //
reg state,next_state;
parameter A=2'b00,B=2'b01,C=2'b10,D=2'b11;

 always @(*)
                2'b00: next_state= in ? B : A;
                2'b01: next_state= in ? B : C;
                2'b10: next_state= in ? D : A;
                2'b11: next_state= in ? B : C;
always @(posedge clk ,posedge areset)
            state<= A;
            state<= next_state;

assign out= (state==D);

It is showing 29 mismatches. Please tell me where did i go wrong. The images of output is as shown

enter image description here

  • \$\begingroup\$ Show us the testbench, please. \$\endgroup\$ Feb 19, 2020 at 12:49
  • \$\begingroup\$ Actually i run the code on HDL bit so the test bench is embedded on the website. So this is all i have got. \$\endgroup\$ Feb 19, 2020 at 12:55
  • \$\begingroup\$ Your HDL actually looks fine at first glance, so I would suspect some sort of disconnect between your HDL and the testbench on the website -- possibly related to port order or port naming. Where is the website? Ah, found it here. \$\endgroup\$
    – Dave Tweed
    Feb 19, 2020 at 13:29
  • \$\begingroup\$ I would suggest adding a probe to your state and next_state variables. You should see the syntax for this in the testbench. \$\endgroup\$ Feb 19, 2020 at 13:35

1 Answer 1


You really need to include an actual link to the website in question — I finally found it here.

Did you read any of the warning messages that the site spits out about your code? They make the problem rather obvious. For example:

Warning (10199): Verilog HDL Case Statement warning at top_module.v(15): case item expression never matches the case expression File: /var/www/verilog/work/vlgNC2KRa_dir/top_module.v Line: 15

This case can never occur. One common bug is that you declared the wrong size for a signal (Also look for warnings about truncating values). For example, case(a[0]) 2'b11: something; endcase never matches because a one-bit signal can never be 2'b11.

Fixing that one problem allows your code to pass all tests.


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