# Designing FSM using Verilog

The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.

My Code

module top_module(
input clk,
input in,
input areset,
output out); //
reg state,next_state;
parameter A=2'b00,B=2'b01,C=2'b10,D=2'b11;

always @(*)
begin
case(state)
2'b00: next_state= in ? B : A;
2'b01: next_state= in ? B : C;
2'b10: next_state= in ? D : A;
2'b11: next_state= in ? B : C;
endcase
end
always @(posedge clk ,posedge areset)
begin
if(areset)
state<= A;
else
state<= next_state;
end

assign out= (state==D);
endmodule


It is showing 29 mismatches. Please tell me where did i go wrong. The images of output is as shown

• Show us the testbench, please. Feb 19 '20 at 12:49
• Actually i run the code on HDL bit so the test bench is embedded on the website. So this is all i have got. Feb 19 '20 at 12:55
• Your HDL actually looks fine at first glance, so I would suspect some sort of disconnect between your HDL and the testbench on the website -- possibly related to port order or port naming. Where is the website? Ah, found it here. Feb 19 '20 at 13:29
• I would suggest adding a probe to your state and next_state variables. You should see the syntax for this in the testbench. Feb 19 '20 at 13:35