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So hello guys I am a first semester student in Computer Science. I have an exam coming up and I couldn't really find an answer whether bubbles affect the delay like inverters.

The bubbles having no delay makes kinda no sense to me since they do basically what inverters do. So I always assumed that there was an invisible inverter where a bubble is. Thanks in advance.

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  • \$\begingroup\$ What kind of bubbles are you talking about? The "circles" you sometimes see at the terminals of a component (see: electronics.stackexchange.com/questions/117828/…)? \$\endgroup\$
    – Huisman
    Feb 19, 2020 at 12:25
  • \$\begingroup\$ @Huisman yes I am talking about those bubbles, sorry like I said I'm just a freshman, I didn't know there were other kinds of bubbles. \$\endgroup\$
    – ninakuup21
    Feb 19, 2020 at 12:32
  • \$\begingroup\$ I would say no. Usually this is built into the gate itself, especially when it is located on the output. AND -> NAND, OR -> NOR, and so on. Even for inputs, the gate can be changed slightly internally to make an inverting input. If the professor never mentioned it I wouldn't worry about it. \$\endgroup\$
    – Stiddily
    Feb 19, 2020 at 12:48
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    \$\begingroup\$ Bubbles are pockets of air (or another gas) in a liquid. From the comments above, what you mean are circles in the schematic. Such a circle means that there is an inverter function. If that adds a delay or not depends on the circuit implementation. So some will add a delay, some will not. \$\endgroup\$ Feb 19, 2020 at 12:48

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Not really.

The "bubble" is a logical inversion. It doesn't necessarily correspond to a physical inverter.

Delay is a property of the physical implementation of a circuit. There isn't really a "standard gate delay" which you can use for all gates at all times. Different logical implementations will have different delay, and it's affected by all sorts of factors including the size of the gates and also the wiring between them.

For the specific case of a CMOS gate, as found in computers, if you were to compare a NAND gate with a bubble against an AND gate without a bubble, and the gates are of comparable size and load capacitance, you would find the AND gate was probably slightly slower. That is because CMOS gates are "naturally" inverting, and tend to be built from NAND/NOR structures as fundamental building blocks.

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The'bubbles' or circles can be found on the inputs and outputs of logic gate symbols. They are used to indicate binary signal inversion - so a logic '0' becomes a logic '1' and vice-versa.

Logic gate symbols are precisely that - symbols. They give no indication of how the logic gate is to be implemented, or what technology is used.

Any delays are going to be a function of the implementation, and as such can't be determined by the presence of inverting 'bubbles'

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