I am designing DDR3 pcb first time so I started from guide about pcb design:
As I understand using only
stripline highly recommended to avoid skew between signal passing top/bottom layer traces and inner layer traces, e.g. using only inner layers recommended to trace DDR3 signals.
But I have to use top and bottom layers to fit in 6 layer PCB. I am using Altium that can match traces length but without differentiation of used layers. So I don't clearly understand is time of flight of signal relative to impedance of trace? E.g. can I avoid worrying about used layers just by using different trace width depending on a layer to keep required impedance so by achieving matching signal lengths I will match signal skews?