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I am designing DDR3 pcb first time so I started from guide about pcb design: https://www.youtube.com/watch?v=ZNq_Ulm8cTk#t=32m As I understand using only stripline highly recommended to avoid skew between signal passing top/bottom layer traces and inner layer traces, e.g. using only inner layers recommended to trace DDR3 signals. enter image description here enter image description here

But I have to use top and bottom layers to fit in 6 layer PCB. I am using Altium that can match traces length but without differentiation of used layers. So I don't clearly understand is time of flight of signal relative to impedance of trace? E.g. can I avoid worrying about used layers just by using different trace width depending on a layer to keep required impedance so by achieving matching signal lengths I will match signal skews?

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  • \$\begingroup\$ No, signal delay depends which layer trace is routed. Normally it should be taken care in any good tool. Altium should take care of this, even though I am not sure about this \$\endgroup\$
    – user19579
    Feb 19, 2020 at 14:15

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So I don't clearly understand is time of flight of signal relative to impedance of trace?

It's not directly related.

Characteristic impedance of a lossless line is given by

$$Z_0 = \sqrt{\frac{L}{C}}$$

where \$L\$ and \$C\$ are the inductance and capacitance per unit length of line.

Propagation velocity is given by

$$v=\frac{1}{\sqrt{LC}}.$$

That means that if you use different geometries that use different values of \$L\$ and \$C\$ to achieve the same \$Z_0\$, you can have different propagation velocity. You certainly can't count on a microstrip and a stripline, both having \$Z_0=40\ \Omega\$, to both have the same propagation velocity.

If you use a transmission line calculator, like Saturn PCB Toolkit or Polar, it will give you the propagation velocity as a separate output from the characteristic impedance. Knowing the propagation velocity, you can adjust the trace lengths of your outer layer traces to match the delay of your inner layer traces if you need to. These results might be slightly inaccurate due to manufacturing variations, though, so DDR layout guidelines often recommend routing all data lines associated with the same byte lane on the same layer.

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