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I want to use Genesys-2 FPGA board as a BER tester for transceiver circuits. I am using IBERT IP core available in Vivado for it. Genesys-2 has an FMC connector to provide output for which I am using SMA-FMC-LVDS of Hightech Global to convert the data from FMC to SMA. Initially, I am connecting transmitter and receiver in loopback just for verification.

The problem is: 1. In loopback connection, in Vivado I am unable to see any transmission. It is only displaying 0Gbps. 2. Previously I have used different SMA-FMC board for which transmission was proper and I was able to measure the BER. By this, it is clear that there is no problem with the code. 3. In the SMA-FMC-LVDS a place holder is provided for an external oscillator. Do I need to solder this oscillator for proper transmission?

I can not find any supporting document for the configuration of SMA-FMC-LVDS.

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From the description of the working board (my emphasis):

Reference clock for the serial transceivers of the carrier board is provided through the module's super clock as well as a pair of SMA connectors for external pulse generators.

From the description of the non-working board:

Reference clocks for serial transceivers are provided through 2 pairs of SMA connectors and external clock generator.

My reading of that is that you do not have a reference clock when using the SMA-FMC-LVDS board, and that's why nothing is working. You can add an oscillator on board (as you say) - it has to meet very tight jitter specifications if I remember right. Or you can inject (again a good low-jitter) clock onto the FMC connectors provided for that clock.

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