Im beginner FPGA Designer.
I need to interface the ADC component: ADS5463. datasheet: http://www.ti.com/lit/ds/symlink/ads5463.pdf with a FPGA (lattice ecp3).
and to understand the inputs & outputs of this ADC, espcially the digital signals: (clk, dry, d[11:0], ovr)
module top( input clk, //clock input = 250MHz input rst, output reg dry, //DRY output reg ovr, //OVR output reg [11:0] d_o; //D[11:0] ); reg [5:0] cs, ns; localparam idle = 6'b000001, start = 6'b000010, busy = 6'b000100, read_middle = 6'b001000, read_end = 6'b010000, done = 6'b100000; //clock input = 250MHz -> Ts=1/fs=4ns localparam t_aperture = 200 , //200ps latency = 8 , //3.5 input clock cycles -> 8 rising+falling edges of clock t_dry = 1600, //950-1600ps CLK to DRY delay t_data = 2100, //750-2100ps CLK to DATA/OVR delay t_skew = 650 ; //-350-650ps: t_data-t_dry: DATA to DRY skew. always @(posedge clk or posedge rst) if (rst) begin cs <= idle; end else begin cs <= ns; end always @(posedge clk or posedge rst) if (rst) begin ns = idle; dry = 1'b0; ovr = 1'b0; d_o = 12'b000000000000; end else begin case (curr_state) idle: start: busy: read_middle: read_end: done: endmodule
what is my job in this kind of design? I need to write onyl state maching based on timing table and connect all the inputs/outputs to the FPGA andd I'll see the right results?
based on the datasheet, on which signals I should have control of? for example DRY is signal which the ADC produce and I should use in my code or I should control it logic levels in my code => take the CLK divide it by 2 and delay it to the middle of the clock?
any Idea how I should build my state machine? seems like I need 3-4 states here: IDLE, BUSY, DONE. any idead how i create 200ps delay with 150-250MHz clk? i thought about just make 1 clk cycle of delay and it will do just fine.. maybe a bit slower that what the datasheet recommends but safe and works.
I would be very glad for any good explanation or piece of code for how to start to do it.