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Im beginner FPGA Designer.

I need to interface the ADC component: ADS5463. datasheet: http://www.ti.com/lit/ds/symlink/ads5463.pdf with a FPGA (lattice ecp3).

I need suggestions how to start implementig it. From my understanding all I need to do is State Machine based on the timing table and graph given by the datasheet: enter image description here enter image description here

and to understand the inputs & outputs of this ADC, espcially the digital signals: (clk, dry, d[11:0], ovr)

enter image description here I wrote a body for the verilog code.. but still think how to really write the logic:

    module top(
    input clk,                       //clock input = 250MHz
    input rst,
    output reg dry,              //DRY
    output reg ovr,              //OVR
    output reg [11:0] d_o;       //D[11:0]
    );

    reg [5:0] cs, ns;

    localparam  idle        = 6'b000001,
                start       = 6'b000010,
                busy        = 6'b000100,
                read_middle = 6'b001000,
                read_end    = 6'b010000,
                done        = 6'b100000;    

//clock input = 250MHz -> Ts=1/fs=4ns
    localparam  t_aperture = 200 ,   //200ps
                latency    = 8   ,   //3.5 input clock cycles -> 8 rising+falling edges of clock
                t_dry      = 1600,   //950-1600ps CLK to DRY delay
                t_data     = 2100,   //750-2100ps CLK to DATA/OVR delay
                t_skew     = 650 ;   //-350-650ps: t_data-t_dry: DATA to DRY skew.


        always @(posedge clk or posedge rst)
        if (rst) begin
            cs <= idle;
        end else begin
            cs <= ns;
        end

    always @(posedge clk or posedge rst)
        if (rst) begin
            ns = idle;
            dry = 1'b0;
            ovr   = 1'b0;
            d_o   = 12'b000000000000;


        end else begin
            case (curr_state)
                idle:

                start:

                busy:

                read_middle:

                read_end:

                done:

endmodule

My Questions:

  1. what is my job in this kind of design? I need to write onyl state maching based on timing table and connect all the inputs/outputs to the FPGA andd I'll see the right results?

  2. based on the datasheet, on which signals I should have control of? for example DRY is signal which the ADC produce and I should use in my code or I should control it logic levels in my code => take the CLK divide it by 2 and delay it to the middle of the clock?

  3. any Idea how I should build my state machine? seems like I need 3-4 states here: IDLE, BUSY, DONE. any idead how i create 200ps delay with 150-250MHz clk? i thought about just make 1 clk cycle of delay and it will do just fine.. maybe a bit slower that what the datasheet recommends but safe and works.

  4. I would be very glad for any good explanation or piece of code for how to start to do it.

Thanks!!

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  • 2
    \$\begingroup\$ Don't jump to using a Finite State Machine (FSM), or any other logic circuit for that matter. Use an FSM because the circuit needs states. Some engineers like FSMs because they can toy with them, adding states and junk until it seems to work but is confusing and hard to understand. Your ADC doesn't have different states. It has predictable, repetitive operation so use a predictable, repetitive counter circuit instead. It'll be much shorter and easier to design, understand and fault-find. Simplicity: simplicity leads to reliability. Read the datasheet again, see the patterns in the ADC bus. \$\endgroup\$ – TonyM Feb 20 at 14:58
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All you need to provide from the FPGA is the clock signal to the ADC. Watch for DRY being asserted, and when it is you can parallel load the 12 data bits and the overflow signal. What happens after that depends on what you intend to do with the sampled data.

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  • \$\begingroup\$ so my state machine is just to wait 3.5 clock cycles and rising edge of dry, after that look for valid outputs from D[11:0]? \$\endgroup\$ – Michael Astahov Feb 20 at 14:46
  • \$\begingroup\$ if you were disgn this adc module.. what would be the inputs/outputs in your code? what I started seems ok? \$\endgroup\$ – Michael Astahov Feb 20 at 14:48
  • \$\begingroup\$ I think by the time your state machine is ready to run the ADC will already have seen many more than 3.5 clock cycles. Just worry about DRY. \$\endgroup\$ – Elliot Alderson Feb 20 at 14:48
  • \$\begingroup\$ You haven't started anything. You don't need to specify all of those time delays and latency. Just look for DRY going high, then store the 12 or 13 input signals that you care about. I have no idea what you want to do if there is an overflow, or what happens to the data after you get it. \$\endgroup\$ – Elliot Alderson Feb 20 at 14:50
  • 1
    \$\begingroup\$ For now there is no use for it.. I just want to see the ADC working \$\endgroup\$ – Michael Astahov Feb 20 at 14:54

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