soc clock domain questions

Question

Those days there have so many different protocols in the soc which basically means different clock rate.

In a Soc system, there have CPU which run at some clock speed, then there have memory(dram) to run at some speed. In between, there have a AXI bus which also has a clock. Is there a relationship between those three clocks? If not, does AXI function as an interface between dram and CPU which transfer the data in the two different clock domain?

If so, how about other domain such as EMMC, HDMI, etc? How can one bus bridge all those different clock domain?

Finally, what will generate the clock for each of those sub-blocks? I know CPU will have its own clock as well as memory as its own clock. How about bus, HDMI, EMMC, SPI, MIPI etc?

THanks a lot,

Brian

Answer 1

One common way is the following:

1. Use a crystal oscillator to create a stable input frequency, perhaps 25 MHz.

2. Multiply the input frequency using a PLL (phase locked loop) with a VCO (voltage controlled oscillator) to get a frequency as fast or faster than all of the required frequencies.

3. Use several frequency dividers (typically arranged in some kind of tree) to produce all the required slower clocks.

For example, if you need a 500 MHz clock, a 300 MHz clock, a 10 MHz clock, and a 1 MHz clock, you could have something like this:

25 MHz --> PLL(x60) = 1500 MHz --> / 3 = 500 MHz
                               +-> / 5 = 300 MHz --> / 30 = 10 MHz --> / 10 = 1 MHz

The exact arrangement of the clock tree often depends on which blocks can be used independently. E.g., in the example above, you could turn off the 500 MHz clock while still running the other slower clocks, but you couldn't turn off the 300 MHz clock without also turning off the 10 and 1 MHz clocks.

Answer 2

SoC Clock Domains

In general, in an SoC using a fabric like AXI, each subunit has 2 or more clocks:

• I/O clock
• Internal block-level clock(s) (if needed)
• AXI (or other interconnect, e.g. Wishbone) fabric

Each transition - I/O to block, block to AXI, is treated a clock boundary crossing. Usually these are separated by a retiming slice like a FIFO or register with handshake.

While having separate clock domains sounds difficult, it actually makes closing timing easier as it localizes the clock-to-clock dependency to the block or I/O domain, rather than the whole chip. This is true whether the various clocks are synchronous or not.

SoC Clock Generation

Complex SoCs with a lot of separate clock domains will use multiple PLLs based on one or more references.

For example, a system with a PCI Express interface will typically have:

• Local clock for the SoC internals (e.g, CPU and AXI) derived from a reference
• PCIe 100 MHz reference clock.

Here, there is a PLL to make PCIe block clocks from 100MHz, and a PLL for the other internals, derived from another reference (e.g., a crystal) for everything else.

The clock generator structure is entirely dependent on the system architecture. Typically it will use once or more PLLs to multiply the reference up to a high frequency (hundreds of MHz to multi-GHz), which is then divided down and / or fed to a frequency synthesizers to make the other clocks.

Refining the above example, a PCIe Ethernet device will have a local crystal feeding a PLL to synthesize the Ethernet MAC+PHY and related clocks, while the PCIe 100 MHz reference from the PCIe host feeds another PLL to make SERDES, PIPE clock and so forth.