SoC Clock Domains
In general, in an SoC using a fabric like AXI, each subunit has 2 or more clocks:
- I/O clock
- Internal block-level clock(s) (if needed)
- AXI (or other interconnect, e.g. Wishbone) fabric
Each transition - I/O to block, block to AXI, is treated a clock boundary crossing. Usually these are separated by a retiming slice like a FIFO or register with handshake.
While having separate clock domains sounds difficult, it actually makes closing timing easier as it localizes the clock-to-clock dependency to the block or I/O domain, rather than the whole chip. This is true whether the various clocks are synchronous or not.
SoC Clock Generation
Complex SoCs with a lot of separate clock domains will use multiple PLLs based on one or more references.
For example, a system with a PCI Express interface will typically have:
- Local clock for the SoC internals (e.g, CPU and AXI) derived from a reference
- PCIe 100 MHz reference clock.
Here, there is a PLL to make PCIe block clocks from 100MHz, and a PLL for the other internals, derived from another reference (e.g., a crystal) for everything else.
The clock generator structure is entirely dependent on the system architecture. Typically it will use once or more PLLs to multiply the reference up to a high frequency (hundreds of MHz to multi-GHz), which is then divided down and / or fed to a frequency synthesizers to make the other clocks.
Refining the above example, a PCIe Ethernet device will have a local crystal feeding a PLL to synthesize the Ethernet MAC+PHY and related clocks, while the PCIe 100 MHz reference from the PCIe host feeds another PLL to make SERDES, PIPE clock and so forth.