# Clock Issues from Buffer

I'm testing a board that is having clock issues. The design uses a 40 MHz oscillator, which outputs a clipped sine wave. The clock goes into an inverter buffer to get a 3.3V, 40 MHz sine wave. When scoping the clock, there is some distortion seen on the positive peaks (shown below). I've noticed that the sine wave is fine before going into the first inverter. The issue pops up on the other side of the inverter. My suspicion is that the inverting feedback resistor value might be the cause of the issue I am seeing, however, I can't find anything that could explain the distortion I am seeing with my clock. I've also read that add a small resistor value to the input of the inverter will help reduce ringing as well. Is that the case and can someone explain to me why/point me to a direction where I can learn more?

Any insight is greatly appreciated.

simulate this circuit – Schematic created using CircuitLab

• how would a buffer convert a clipped sine to a sine wave? Also, are you sure your FPGA even wants a sine wave? Feb 21, 2020 at 23:37
• All these harmonics can be explained by trace and probe ground inductance with inverter + circuit capacitance Feb 21, 2020 at 23:50
• Characterizing clocks on boards is not easy. The best method that I have found requires planning ahead and serious money. Put a signal pad and a ground pad near each other, as close to the destination as possible. Then use a FET probe to probe these two pads. Only a well-funded lab can afford the probe: tek.com/low-voltage-probe-single-ended#product-list Feb 22, 2020 at 7:50

If you want textbook waveforms then you must use proper probing techniques with non-inductive grounds and good C decoupling on the chip. 5V Logic is 10x faster than CD4xxx logic and 3.6V logic even faster.

Your waveform appears to be 3.3V logic with overshoot due to 10:1 probe ground inductance and resonance and false measurement well over the supply . The 250mVpp reading appears incorrect as the scale is 1V/div and peak reading well above expected clamp levels due to measurement error.

There is nothing wrong with the circuit, but controlled impedance traces will look better. this means reducing the 100k feedback so that the stray load capacitance is not limiting the rise time ~1~2ns 10-90% of steady state levels.

The performance is controlled by the signal at Vdd/2 and not so much with the harmonics. Tr=0.35/f(-3dB)

What IC , layout did you use for testing? What are your expectations?

If your goal is to have a Schmitt snap-action input (turn sine into square), then R1 needs to be connected after the second buffer (that is, positive feedback.)

Or (choose one):

• change the inverter to non-inverting type
• change the inverter to a Schmitt-trigger type, and add a midpoint bias
• he is using non-inverting and hysteresis will not improve rise-time or harmonic measurement error. -1 Feb 22, 2020 at 3:41
• Look again. The buffers are inverting, and there’s feedback on the first one. I don’t think that’s the OP’s intention. To convert sine to square, there should be a Schmitt in there, whether by external snap-action feedback or an honest-to-goodness Schmitt buffer. Feb 22, 2020 at 22:02
• My bad. I did not mean to say non as you suggest which gives 2 stages of gain vs buffered inverter which has 3stages. All you need is a gain of 10, and 1 ns rise,fall times for 50MHz with Ron=25 Ohm in 3.6V Logic @ 3.3 V with 30 pF Load, depending on driver sitime.com/api/gated/AN10022-rise-and-fall-time.pdf see table 5 , but no hysteresis. Feb 22, 2020 at 22:18