I am working with LWIP - and an 1G marvell phy, m88e1111 - connected to a Microsemi SmartFusion 2 FPGA design using 10b8b (aka: TBI) interface.
I'm doing something wrong with the auto negotiation and it's probably mostly me, I can't find things that answer my questions.
The internal SGMII phy (in the FPGA) is at MII address 30, the external PHY is at address 7.
The external phy (Marvel m88e1111) is configured via pull up/dn to auto connect on power up and auto-negotiate - This works great with the switch.
It's the INTERNAL phy to the Marvell negotiation that seems to fail (50% of the time) that is a problem and prompts my questions.
When I hunt for docs on the web (google) - I find detail about the process but what I find assumes a lot of pre-knowledge, and I don't find a "for dummies" doc anywhere.
1) Is there an order that I should follow when bringing up an interface? Am I required to wait for the External PHY to complete, before I can start the SGMII negotiation?
2) How long should I wait for the auto-negotiation to complete before I declare a timeout? Once enabled, do I need to restart it again and again?
3) my current system works as follows:
Step 1 After power up - on a timer, every 2 seconds I poll the external phy (I do not have a PHY interrupt)
QUESTION: Is 2 seconds right? Should it be longer?
Step 2 - Wait for external phy to "complete" (link up bit) Typically takes 2 to 5 seconds after reset, and is rock solid.
Step 3 - After ext-phy complete, I test the SIGMII status the link is down, so I start the internal to external negotiation.
I repeat this on the every 2 second timer until I see link up.
Problem: sometimes it takes 20 seconds (10 tries, often more ) to get the SGMII connection up, this seems just wrong, really wrong.
Sometimes (5% case) it takes less then 1 second, I'm expecting 1 second but 95% of the time it is more like 10 to 20 seconds
Question: How long should auto negotiation take? Am I doing something in the wrong order? Or cutting the timeout too short?
Note: I have no means to test (signal integrity) between the FPGA and the external PHY... I don't have a $300K scope at my disposal.
Question: Are there test/debug registers I can use? The Marvell one has something that outputs a test pattern but I don't see any means to tell the other phy, or things like that to "tell me how good the test pattern is"