# Freerouter doesn't want to route to inside an FPGA

Prefacing this by saying I'm entirely new to designing electronics for a PCB and I've only worked with breadboards before, so if there's more that I'm doing wrong in my project besides just the PCB design I would be very appreciative if you let me know.

I'm trying to use an iCE40HX8k-CT256:

For example, there are multiple I/O bank power pins connected to the same source (I haven't finished drawing the symbol):

VCCIO_1_1 and VCCIO_1_3 are connected in the schematic, and as such are connected by a rats nest line in Pcbnew:

Freerouter absolutely hates trying to route connections inside the FPGA, including the example above:

What am I doing wrong? How can I make it so that Freerouter wants to and is able to route outside connections to inside of the FPGA?

If it helps, the current KiCad source is up at https://github.com/bgec/bgec-hw.

The thin line around your pads represent the resulting clearance from your board setup and net clearances. The same with the light gray area drawn around a trace while you route it.

There simply is no space left between the BGA pads for any feature to go with your current clearance and size setup. Double check if you can reduce the clearance and still fulfil the manufacturing requirements. This might mean you need to select a more expensive process.

Fine pitched BGAs might require tight tolerances for manufacturing and possibly options like micro vias or via in pad. Talk to your manufacturer what the cheapest option is.

An alternative is to check if your component is available in a different package or if there is a ready-made module that you can incorporate in your design. (Might be cheaper than choosing a BGA capable process especially if you only make a few products)

• I tried enabling microVias in Pcbnew and I have no option to place them, even with more than 2 layers like an online forum thread said. Many local manufacturers I am looking into support and have measurements for small enough holes, but I only want to use smaller-than-default holes when necessary. I might be able to choose the TQ144 that comes in TQFP over the CT256, and that should work better, correct? – Soren Feb 22 at 10:19
• Microvias are placed via the hotkey ctrl+v (or by choosing micro via from the right click context menu) while you lay down a trace (similar to how normal vias are generated) Be aware that micro vias typically only span two layers. But even with microvias your clearances might still be too large to get a trace to the micro via. – Rene Pöschl Feb 22 at 11:00
• I tried C-v and all it did was switch layers :/ I think I'm gonna give the TQ144 a shot as its working so far ( cdn.discordapp.com/attachments/480711423681495047/… ) and if I don't run out of pins I'll mark this solution as correct ("...check if your component is available in a different package...."). – Soren Feb 22 at 11:49
• What happens if you right click and select micro via? Maybe your operating system does not allow the hotkey combination to reach KiCad. (If it does not work with the right click option then try it where you definitely have the space, maybe even a micro via is too large with your current settings for clearance. Also make sure you have enabled micro vias.) – Rene Pöschl Feb 22 at 11:59
• Also consider that it might not be the case that the micro via is too large but that the trace connecting the pad to the via is too large. (If the interactive router does not find a way to place a trace then it will not allow the placement of the micro via.) In other words if you can not lay down a trace to the location where you intent your via to be then you can not place the via there no matter how small the via itself is. – Rene Pöschl Feb 22 at 12:08

Your traces might be too wide to fit between the pins without violating design rules. The vias are definitely too big.

Try routing that trace manually and see what happens. If you can't do it manually, the autorouter likely won't be able to either. If you can do it manually, then you can always just let the autorouter do as much as it can and clean up the rest manually.

It wouldn't be unusual to route a simple board like this entirely manually. I'd even say it would be best to do it manually if this is a first-time learning exercise. That way you can get a feel for how the process works and how all the rules work. After that you'll be better equipped to figure out what's going on when the autorouter fails.

• So far I've been unable to do it manually. I think the reason is that KiCad thinks I'm trying to route all the pins between them together because I'm unable to connect layer one to layer two and then go under layer one. That poses an interesting problem though: If I can go completely vertically, should I just add layers to get routing working until I won't run into collisions? – Soren Feb 22 at 9:29
• Yeah, I don't have enough room to place a "via". Am I able to use smaller track and via sizes than the defaults? Are there standard sizes I should be using? – Soren Feb 22 at 9:34
• consult your fabhouse, some maybe able to go downto 6thou and then you stand a chance IF you limit that to routing out from the BGA. also consider turning the fpga by 45deg to improve fanout – JonRB Feb 22 at 10:08

The LP8K is only available in 0.4 mm spacing BGA The HX8K is already the bigger spaced 0.8 mm BGA - if the HX4K is an option as well the 144 TQFP might be a solution. If you want to stick to 8k logic cells: From personal experience with the 0.4 mm spacing BGA I can tell that there are basically two routes from here: the expensive I-want-it-all and the challenging compromise. The former involve the use of VIA in PAD technology, blind/burried vias, and more than four layers which can be very expensive. The latter is based on some tricks and compromises:

Some manufacturer offer a fair price for 4 layer, 0.1 mm tracks/clearance and 0.2 mm vias. With that a VIA fits exactly underneat a pad (note: KiCADs design check tests for "bigger than the minimum" so one has to slightly decrease the BGA pads size to e.g. 0.198 mm so that the DRC is not triggered). If one place a VIA under one pad one cannot place another left/right/top/bottom from it; but diagonal from it! I commonly use adjacent pads to place a via there and then prohibit the use of the pad in the design. This is similar to the typical dog bones. One has to be careful not to use any dual purpose/system pins as they can have a different functionality during boot up and user code phase.

If one does NOT use a dog bone like approach but a VIA directly underneath the pad to connect one has to make sure that the solder from the ball is not simply drawn into the hole of the via during the reflow. This can be done either with via-in-pad or filled vias (costly) or one can do the "poor man's" filled via by taking the PCB before assembly, turn it top faced done and use solder+solder iron to fill the vias from the backside with solder. This way the solder from the BGA is not drawn into the holes anymore.

However with 0.1/0.1 technology and 0.2 vias without blind/burrowed you will be abled to at most route out 3 "rings" of pads from my experience (first ring can be directly accessed from the top layer, second from one inner layer, third can be typically routed around the vias of the "second" ring but there is normally no space for a "fourth" group as the through VIAs of the second and third already blocks all pathes). So routing all pins/pads will require the costly approach for sure and one can use in most cases a lower pin count BGA as one has to leave out most pins anyway.

Welcome to the joys of BGA's.

Quickly capturing your part, power rails and some token IO

NOTE: not the greatest symbol but for a quick auto-generated it will do. NOTE I would have broken these into banks

Here is a crude placement

And zooming in:

Exactly your concerns, but these are kicad defaults. Assuming you would go for a 4layer PWB (not sure it is viable going for a 2layer with such a BGA...) and cross-checking with a fabricator:

https://docs.oshpark.com/services/

All 4 layer boards ship with FR408 substrate, purple mask over bare copper, and ENIG (immersion gold) finish.

5 mil (0.127mm) trace clearance

5 mil (0.127mm) trace width

10 mil (0.254mm) drill size

4 mil (0.1016mm) annular ring We do not support blind or buried vias.

Updating the design constraints produces:

This is now routable. Also consider 45Deg rotation. Not only does it look nice, but helps with tracking out