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Recently I had to build a h-bridge driver for my project, wireless power transmission. I learnt that I needed to have dead-time in my PWM signal given to IR2110, which doesn't have any dead-time control function. As my model only requires below 200kHZ, I had to code the arduino uno which I used to generate the pwm signal, to have dead-time. My brain got stuck in a question, what is the difference between the generic mosfets and the mosfets/transistors used inside the processor? As modern CPU clock is nearly 5GHz while a normal CPU can have a clock of around 3Ghz. So how does they do it?

How do they reduce the turn-off delay in CPU? How do the mosfets inside a CPU switches so fast while a generic mosfet like IRFZ44N have a turn off delay time of 44ns according to the datasheet?

Thanks.

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    \$\begingroup\$ If your question is how the Arduino generates dead time delays with such fast transistors : it does it by counting a number of clock cycles between turting one output off and another on. \$\endgroup\$ – Brian Drummond Feb 23 at 16:19
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    \$\begingroup\$ How do they go so fast, or how do they not burn up from shoot-through current? \$\endgroup\$ – TimWescott Feb 23 at 16:23
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    \$\begingroup\$ @BrianDrummond I think I described the question in a bad way. I wanted to know how the fets inside a CPU work in so much speed while I have to take care of dead time when using a h-bridge? \$\endgroup\$ – Aimkiller Feb 23 at 16:27
  • \$\begingroup\$ @TimWescott yeah, both I meant \$\endgroup\$ – Aimkiller Feb 23 at 16:27
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    \$\begingroup\$ Could you edit your question to reflect that? It's a StackExchange thing -- they don't want bits of question embedded in the comments. \$\endgroup\$ – TimWescott Feb 23 at 16:30
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MOSFET load drivers are much, much larger than the FETs used on a CPU chip: they have to be to deal with the voltage and current they’re designed to drive. As a consequence of their size they have large gate capacitance and so take longer to change their gate voltage from ‘on’ to ‘off’ state. Also, to achieve low Rds(on) appropriate for a driver, they need higher Vgs(on) than a CPU FET. This adds even more to the charge burden, and thus the switching time.

In contrast, CPU transistors are physically small, work at low voltage, and are driving relatively tiny on-chip loads. They have small gate capacitance and a low Vgs(on) so they can switch very quickly. They’re also sometimes allowed to have an extra-low gate threshold and even a bit of leakage, so the gate voltage swing needed to switch them is reduced even further.

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  • \$\begingroup\$ I see. This explains my problem. Thank you! \$\endgroup\$ – Aimkiller Feb 23 at 16:28
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    \$\begingroup\$ Much larger as millions or billion time larger surface area \$\endgroup\$ – TEMLIB Feb 23 at 18:46
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    \$\begingroup\$ Transistors in a CPU can be very imperfect. All that’s really required of them is to be small and switch fast. They don’t need clean edges, they don’t need to switch high currents, they don’t need to survive high voltages and so on and so forth. In the recent decade leakage current has become more important, but for critical paths the synthesis tools can automatically “upgrade” to faster (Ultra) Low Voltage Threshold cells. \$\endgroup\$ – Michael Feb 24 at 10:23
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    \$\begingroup\$ nitpick: a MOSFET driver is an IC responsible for driving the gate of a power FET. I think you meant "power MOSFETs" there. \$\endgroup\$ – Hearth Feb 24 at 19:47
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    \$\begingroup\$ What you’re describing is a MOSFET gate driver. Which is itself, a kind of driver which can (but not necessarily) use big MOSFETs in its driver stage. Which will have drivers on-chip to deal with that big final stage... and down the rabbit hole we go. \$\endgroup\$ – hacktastical Feb 24 at 19:57
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The construction of the MOSFETS in a logic chip is generally very different from the construction of discrete MOSFETs. A typical discrete MOSFET will actually be constructed as a very large number of MOSFETs wired in parallel, which will be arranged with the drain and gate contacts on one side, bulk contact on the other, and with the source regions tied to the bulk region. Having only two kinds of contact on one side instead of all three greatly facilitates wiring all of the devices on the chip in parallel.

Using this sort of geometry within a chip, however, would make it necessary to tie all of the sources or all of the drains together, which would greatly limit the range of useful circuits one could create. Instead, logic chips generally use transistors whose source, drain, and gate are both located on the same side of the chip, isolated from the bulk contact. This would make it much harder to wire many transistors in parallel, but since relatively few transistors within a logic chip will be wired in parallel that's no big loss.

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