Im trying to build ADC interface with FPGA.
Im using ADS5463: http://www.ti.com/lit/ds/symlink/ads5463.pdf
after getting some help here I wrote a simple verilog code that just waits to DRY which is the adc clk to rise and output the data, here is my code:
module top( input rstn, input dry_i, //DRY=fs/2 -> fs=160Mhz -> DRY=80MHz input ovr_i, input [11:0] d_i, output reg ovr_o, output reg [11:0] d_o ); reg [2:0] cs, ns; reg dry_i_r; reg [11:0] d_o_r; reg ovr_o_r; reg rst; localparam idle = 3'b001, busy = 3'b010, done = 3'b100; always @(posedge dry_i or negedge rstn) begin rst <= ~rstn; end always @(posedge dry_i or posedge rst) begin if (rst) begin cs <= idle; end else begin cs <= ns; end end always @(posedge dry_i or posedge rst) begin if (rst) begin ns = idle; d_o_r <= 12'b000000000000; end else begin case (cs) idle: begin ns = busy; end busy: begin if (dry_i) begin d_o_r <= ~d_i; d_o_r[10:0] <= d_o_r[10:0]; ovr_o_r <= ovr_i; ns = done; end else begin ns = idle; end end done: begin d_o <= d_o_r; ovr_o <= ovr_o_r; ns = idle; end default: begin ns = idle; end endcase end end endmodule
The reson why I inverted the MSB is because i read here: https://en.wikipedia.org/wiki/Offset_binary
that inverting the MSB converts it to 2s compliments which is easier to work with in Matlab later..
which is seems like just a stable while I provding sine wave for the ADC.
another simulation made it just go from 000 to 800 which also seems not right
Any idea how to make it work? How you would wrote this ADC Interface code?
after the help and a little more thinking.. I just made the code very straight forward and simple.. and I get the sine wave I wanted in the Matlab simulation (binary to decimal and substract by 2048):
module top( input rstn, input dry_i, input ovr_i, input [11:0] d_i, output led_clk, output reg led_data8, output reg ovr_o, output reg [11:0] d_o ); reg rst; reg [25:0] adc_clk_count = 26'b0; always @(posedge dry_i or negedge rstn) begin rst <= ~rstn; end //LEDS FOR OUTPUT TESTING: assign led_clk = adc_clk_count ; always @(posedge dry_i or negedge rstn) begin if(~rstn) begin adc_clk_count <= 26'b0; end else begin adc_clk_count <= adc_clk_count + 1'b1; end end always @(posedge dry_i or negedge rstn) begin if(~rstn) begin led_data8 <= 1'b0; end else begin led_data8 <= 1'b1; end end always @(posedge dry_i, posedge rst) begin if (dry_i) begin if (rst) begin d_o <= 12'b100000000000; ovr_o <= 1'b0; end else begin d_o <= d_i; ovr_o <= ovr_i; end end end endmodule
matlab simulation (analog):
my next challange is to make it work with DDR clk.. I will ask another questions in the future if I will need more help, thanks for now.