My counter for my cpu stack alternates between counting up and down

Question

My Counter for my cpu stack is given the up signal at the same time it is given the clock pulse to advance. This happens on the pull from stack instruction so the counter goes back up the stack one and gets th right address..

But here is the thing, even though the clock and up signal are both true at the same time it alternates between counting up one and counting down one. i'm not sure why as it works when testing it normally with a constant 1 for up and ticking the clock myself.

EDIT: Just tested the instruction in the chip. and for some reason i get a different thing happening. When setting the first 8 bits of FP to 00001110 (Pull from stack) the counter counts down to FFFF, but then the next time i set 00001110 it jumps to 2 for no reason and to 1 and to 0 then to ffff and repeat. there is no way this is not a bug in circuitverse... plus it should be going up not down.

Here is a link to the sim if you wanna look at it. https://circuitverse.org/users/17603 The chip is called "Stack".

Here is a image of the systemm

Answer 1

Are you violating setup or hold timing constraints on the Up/Down input?

If U/D is changing at the same time as clk, you can't be sure if the old or the new value of U/D is seen - it is even possible that part of the counter sees Up and the rest sees Down. As you can imagine, the counter won't work reliably if that happens.

You need to setup U/D some finite time BEFORE the clock edge and hold it at that same level for some finite time AFTER, to guarantee seeing the right level when the clock actually happens.. Failing to do these is called "setup and hold violations".

What the correct setup and hold times are, I can't tell you. For old fashioned TTL logic there was a fat book with a bright orange cover called "The TTL Databook", with about a thousand pages of setup and hold timings and other data for every logic IC that Texas made.

You'll need to find out what the equivalent timing parameters are for this system, and keep U/D stable throughout this time window. You can change it at any other time.

In FPGAs, the timing analysis tools do a very good job of warning if you have accidentally violated one of these timings, but you still have to fix it yourself. There are a basic set of "synchronous design rules" that help avoid almost all of these problems : they all basically come down to "don't do that" (clock and other signals at the same time).

In your system I have no idea how that all works; hopefully now you know you're looking for such a thing, it'll be easy to find.