# Modification to the D flip-flop

When we take a clock and a signal, the D flip flop output always gives "clock edge" AND, and the state will be high unto to the next clock cycle. Now I want my output like like a latch, but timing will be determined by the corresponding clock signal.

If we think about the case 1 (input 1 = D), we do not get any higher state because the clock is not on. But latches gives output (case 2 when D = input2) in this case when both state is high, i mean the clock and input. But the problem is that latches don't give the clock leading edge time.

Is there any way I can get the state high from the corresponding clock leading edges all the time, while it works like a latch? Like the last output that I have added in the diagram.

• You want this device you're proposing to know when the clock edge arrives, that the input is about to change to 1, some few nanoseconds after the clock edge? Feb 24, 2020 at 5:42
• Your question is not clear. Ignoring the Preset and Reset inputs that override the D function, a D flipflop has only one input (the D input), and two outputs that always are complimentary (Q and Q-). Feb 24, 2020 at 5:43
• You know what they say: "It's very difficult to make predictions, especially about the future." And this is just as true for logic circuits as it is for people. Feb 24, 2020 at 5:44
• The two INPUT works like two cases of D (input). Feb 24, 2020 at 5:45
• If we think about the case 1 (input 1 = D), we do not get any higher state because the clock is not on. But latches gives output in this case when both state is high, i mean the clock and input. But the problem is that latches don't give the clock leading edge time. Feb 24, 2020 at 5:48

D flip-flop is used for synchronizing input with clock. The complementary Q and Q# outputs are determined by the input value "at" the clock edge. The input must be stable during a specified time interval around the clock edge (setup and hold time). The input value is irrelevant except during the sampling interval, defined by setup and hold time. So in your figure, the pulse on the input1 trace is briefly high during the falling edge of CLK, but it is low during every rising edge of CLK. So output1 (Q1) is therefore always 0. The input2 trace has a pulse that is 1 during the rising CLK edge that is highlighted, so output2 (Q2) is 1 for one clock cycle. Effectively the D flip-flop behaves like a 1-cycle delay element, synchronizing an input signal into the CLK timing domain.

We say that the D flip-flop input is "sampled on the rising edge of CLK", meaning that relative to the moment when the CLK signal rapidly changes from logic low to logic high, for a "setup time" duration before that event, and continuing through a "hold time" after the rising edge, the D input must remain at a valid, constant logic level. Whichever logic level D is in, determines the Q/Q# output logic level for the subsequent clock cycle.

I think you may be trying to sample the input1 trace on the falling edge of CLK, instead of the rising edge of CLK. Correct?

Depending on how the circuit is realized, it may be possible to select a falling-edge triggered D flip-flop, or else an inverted CLK can be used. Setup and hold time interval would be relative to the falling edge of the clock instead of the rising edge.

• I'm trying to sample the input1 with the leading edge of the CLK. Feb 24, 2020 at 10:30
• But in your example, input1 is always low during the leading edge of CLK (i.e. the rising edge), it is only ever shown high during a falling edge of CLK. Also, if the vertical blue line represents a single synchronous moment in time, then the "expected output1" seems to be reacting before input1. Electronic devices can't look ahead in time. Feb 24, 2020 at 10:55

Blockquote I'm trying to sample the input1 with the leading edge of the CLK> Blockquote

That is exactly what a D flipflop does. Don't confuse it with the action of a "transparent latch", which is not the same thing. With a simple D ff, the output does not change with activity on the D input. It changes only with the correct direction clock edge, and then only if the D input is different from the Q output. The output is latched to the current state of the D input at the moment of the clock edge.

• But can't we register every clock information? for example, once CLK and input 1 is both high, the registered edge of the CLK will set the time? Feb 25, 2020 at 0:31