D flip-flop is used for synchronizing input with clock. The complementary Q and Q# outputs are determined by the input value "at" the clock edge. The input must be stable during a specified time interval around the clock edge (setup and hold time). The input value is irrelevant except during the sampling interval, defined by setup and hold time. So in your figure, the pulse on the input1 trace is briefly high during the falling edge of CLK, but it is low during every rising edge of CLK. So output1 (Q1) is therefore always 0. The input2 trace has a pulse that is 1 during the rising CLK edge that is highlighted, so output2 (Q2) is 1 for one clock cycle. Effectively the D flip-flop behaves like a 1-cycle delay element, synchronizing an input signal into the CLK timing domain.
We say that the D flip-flop input is "sampled on the rising edge of CLK", meaning that relative to the moment when the CLK signal rapidly changes from logic low to logic high, for a "setup time" duration before that event, and continuing through a "hold time" after the rising edge, the D input must remain at a valid, constant logic level. Whichever logic level D is in, determines the Q/Q# output logic level for the subsequent clock cycle.
I think you may be trying to sample the input1 trace on the falling edge of CLK, instead of the rising edge of CLK. Correct?
Depending on how the circuit is realized, it may be possible to select a falling-edge triggered D flip-flop, or else an inverted CLK can be used. Setup and hold time interval would be relative to the falling edge of the clock instead of the rising edge.