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The preferred decaps for the power pins in the Ic is one smaller value, say 0.1uF and one bulk value like 10uF. But for FPGA there are several power pins in one IC, if I have to provide decap for those power pins: 1. weather one smaller and one higher value capacitor is enough for all the power pins? or 2. Should i have to give two value(smaller and bulk) capacitor for each power pins? 3. weather i can give smaller value to each pin and single higher value decaps as shown in attached image? enter image description here

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    \$\begingroup\$ first reference should be reference manual or the datasheet of the part \$\endgroup\$
    – User323693
    Feb 25 '20 at 7:57
  • \$\begingroup\$ Most FPGA vendors will have recommendations, often depending on the package and speed grade. These recommendations are usually more then slightly overkill, but caps are cheaper then board respins. Generally it amounts to many, many 10n or 100n caps plus a few much larger bulk caps. Do be careful of overly low ESR, sometimes a small amount of series resistance is your friend (And you can actually buy MLCCs with specified ESR for this use). \$\endgroup\$
    – Dan Mills
    Feb 25 '20 at 11:38
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It is generally recommended to have decoupling on each individual power pin.

If two pins are next to each other or very close then you can also let these pins share the same decoupling capacitor(s). But if there is enough space on the PCB, the preferred option is still to have decoupling on each individual power pin.

It is also recommended to use a small value (100 nF for example) capacitor and a large value (1 uF or larger) in parallel to get better decoupling. Why this is so is explained by Dave in this EEVBlog video.

It is recommended to place the small value capacitors as close as possible to the IC's power pins. The reason for this is to keep high-frequency loops small to minimize supply ripple and RF emissions (EMI). The small value capacitor works better at high frequencies so its placement is more critical.

You can compromise on the large value capacitors and place fewer of them and only place them where it is convenient.

Decoupling (or bypass) capactitor selection isn't an exact science, most experienced designers just follow the basic rules as stated above, look in the datasheet of the IC what is recommended, copy what is done in other designs and use common sense.

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You want a capacitor pair(small and bulk) for each power pin, the value depends on many factors so I cannot tell you what is best with the current info, the values you mention do sound typical to me.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/operation-and-testing/power/pow-integrity.html

I suggest you read this if you can, there is a physical purpose why you place a pair as close as you can to each power pin.

edit: there are other posts discussing similar topics worth a read

Why too many capacitors in parallel for Vdd supply net? Can't we just add all to replace with one big capacitor?

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In general you want 1 small decoupling cap per power pin. You might be able to get away with 1 for every 2 or 3 pins if there is a very large number of pins and they are all close together. The main thing to keep in mind with decoupling caps is you want to get them as close to the pins as physically possible to minimize the inductive loop and path lengths.

In some cases, multiple capacitors of different values connected in parallel are recommended. In this case, the smaller one must be placed closest to the pins. If there is a very large number of pins, you might be able to get away with fewer of the larger value cap, as they help more at lower frequencies and as a result can tolerate a bit more inductance from the interconnecting traces.

Bulk capacitance should be placed near the chip, but doesn't necessarily need to be near the pins.

You may also want to provide separate/more careful decoupling for more sensitive supply rails such as analog supplies, PLL supplies, serializer supplies, etc.

As usual, check the documentation for recommended decoupling methods.

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