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I am trying to learn some low level implementation so I have been trying to interface to a SAM D09 micro-controller via the SWD interface. I have the chip on a board and I am driving GPIO. I have found that if I use the Extended CPU Reset in accordance with the uc manual, followed by 50 clocks of SWCLK with SWDIO high and 2 clocks of SWCLK with SWDIO low, followed by read IDCODE(b'10100101), then a turnaround(set SWDIO to high-impedance on my host) the uc responds for the next 28 clock cycles on SWDIO however it is not at all what I expect nor does it seem to conform to the SWD protocol. It always seems to respond with 0xBF321F0. This would appear to respond to have both the WAIT and FAULT bit on in the Acknowledge phase. I cant seem to find any information on whether I need to do anything else to initialize the SWD

EDIT

This is my complete sequence

x denotes the line is high impedance, SWCLK indicates the count of SWCLK going high, SWDIO is the state of SWDIO stable

-------------------------
|SWCLK Cycle|SWDIO Value|
-------------------------
|           |Host Driven|
-------------------------    
|          1|      1    |
|          2|      1    |
.......
|         48|      1    |
|         49|      1    |
|         50|      1    |
|         51|      0    |
|         52|      0    |
|         53|      1    |  <- Start of read IDCODE
|         54|      0    |
|         55|      1    |
|         56|      0    |
|         57|      0    |
|         58|      1    |
|         59|      0    |
|         60|      1    |
|         61|      x    |  <- One cycle turnaround(SWDIO is changed to input on host)
-------------------------
|           |Trgt Driven|
-------------------------
|         62|      1    | <- Start of Target response
|         63|      0    |
|         64|      1    |
|         65|      1    |
|         66|      1    |
|         67|      1    |
|         68|      1    |
|         69|      1    |
|         70|      0    |
|         71|      0    |
|         72|      1    |
|         73|      1    |
|         74|      0    |
|         75|      0    |
|         76|      1    |
|         77|      0    |
|         78|      0    |
|         79|      0    |
|         80|      0    |
|         81|      1    |
|         82|      1    |
|         83|      1    |
|         84|      1    |
|         85|      1    |
|         86|      0    |
|         87|      0    |
|         88|      0    |
|         89|      0    |
|         90|      1    |
|         91|      1    |
|         92|      1    |
|         93|      1    |
|         94|      x    | <- Line returns to high impedance
|         95|      x    |
|         96|      x    |
|         97|      x    |
.......```


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  • \$\begingroup\$ I'm not sure how the waveform should be posted but the 28 clocks after one clock after the IDCODE read command are b'10111111001100100001111100001111 \$\endgroup\$ – MDK Feb 26 at 16:06
  • \$\begingroup\$ I edited my question to hopefully clarify the timing \$\endgroup\$ – MDK Feb 26 at 16:37
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If I rewrite it horizontally I get:

             4 5         6         7         8         9
             8901234567890123456789012345678901234567890123456
host:  rrr...rrr  SARaaPpK                                
hi-z:                     t                                ???
trgt:                      AAA?????????????????????????????
swdio: 111...1110010100101x10111111001100100001111100001111xxx

Your whole transaction seems strange.

Three first bits shifted out by the target (62-64 in your trace) are Acknowledge bits. They should have only one bit set (either Ack, Wait or Fail). You get 101, which is not defined at all by SWD spec.

Then if low impedance really happens on bit 94, you have too few data phase bits. There should be 33 (32 data + 1 parity). You have only 30.

Some leads:

  • you may have some ringing on SWCLK line, and target interprets one rising edge as multiple (this would shorten the transaction like this),
  • you may be running this too fast (I would suggest to avoid running above 1MHz for enumeration).

In all cases, hook-up some logic analyser (or even better, a scope, to see Hi-Z) to understand what happens.

| improve this answer | |
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  • \$\begingroup\$ I have slowed it down to 20Hz and I still get the same result. What I'm trying to figure out is if this is something to to with booting up in Dormant mode. There also seems to be a SWDv2 in which a TARGETSEL must be written but I can't find any documentation on whether this is the case on my uc \$\endgroup\$ – MDK Feb 26 at 17:38

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