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How can the state of the registers upon PoR can be managed? My first idea was to detect the reset and manage the state inside a state machine, but I suspect the solution is not optimal. Are there any technology or architecture specific ways to manage this?

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For an SRAM based FPGA, when the device comes out of power-on reset, it is blank. No design is loaded. After a power-on reset, the FPGA configuration logic will load the design onto the FPGA and start it running. Usually during this process, all of the registers will be loaded with initial values (usually 0, but for many FPGAs you can use initial blocks or inline initialization to set these values) and you can simply set the initial value of the state registers to be the appropriate idle or reset state. If you use PLLs or other clock management components in your design, you may need to use the 'locked' outputs from those to derive reset signals for your design - in this case, there would be no difference between a power-on reset and a reset from a PLL losing lock.

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It depends on what type of FPGA you are using. For instance flash based FPGA's has initialization monitor IPs. You can monitor each bank calibration status, device initialization status and POR.

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