At this point in time it doesnt really matter, while technical in nature you can consider this a marketing thing, a way to make motorola look better than intel, we have memory mapped I/O and a flat address space. Which kicked off a chain of events we still feel today.
Addressing is addressing. 123 main street in smith town could be an apartment complex. 123 main street in jones town, could be a house, either can hold people, a dog or a cat, a car in the garage, a large swimming pool in the back. Does it matter that one is an apartment or a house if you are interested in mailing something to a specific individual? Or you are a paving crew putting in a new driveway? No it doesnt. Does it matter if you drove to that dwelling by turning right on to main from 1st street or left from 2nd street? No, you just need to get to the right address.
Think in terms of modules, the processor is a module it has a bus that bus has control signals and address and data at a minimum. Some way to indicate a write or a read, todays busses are more complicated (essentially separate read address, write address, read data, write data busses) but still provide a divisible boundry. Then you have your first level address decoders and here is where the address space starts to form, there are generally a few to several to many layers of address decoders. I need to decode the country, then the state, then the city, jones town or smith town, the the street and then finally the address of the dwelling on that street. I might have the address 0x41100123 vs 0x41200123, as a designer of the chip I may have arbitrarily decided that addresses in the 0x40000000 to 0x4FFFFFFF range are where I am going to map my peripherals. And I decided that 0xx1xxxxxx is a certain sub space within 0x4xxxxxxx lets call it the state that jones and smith towns are in. and 0xxx1xxxxx indicates jones town and 0xxx2xxxxx indicates smith town and 0xxxxx0xxx indicates main street and 0xxxxxx123 indicates the address on that street so 0x41100123 is 123 main street in jones town and 0x41200123 is 123 main street in smith town. Now does everything have to have a main street? Nope, in this case perhaps think of this as two separate uarts and I want to access the status register in uart 0, I have decided as the designer, arbitrarily there is no grand science to this, that 0x41100123 is the status register for uart0, and 0x41200123 is the status register for uart 1, if I were to add a uart2 to my design later on if I have left room I would naturally put that at 0x41300123. So what I decided in my design was that 0x40000000 is where the peripherals start in the very early address decoder right on the edge of the chip I can route those accesses toward a peripheral address decoder, then within the peripheral address decoder bits 27:24 indicate that this is one of the uarts, so I push down into that decoder, then that decoder examines 23:20 to determine which uart, then the lower bits are examined by the individual uart. Each of these address decoders puts enables on the sub busses to indicate this address is for you. This address is for the chip comes from the processor, the first level in my design has examined the address and enabled on a peripheral bus this address is for the peripherals, then the next level this address is for the uarts, then the individual uart has its bus enabled with an address and it simply does what it is told
flash on my microcontroller say I choose to design it with four 0x1000 byte flash banks. and I choose primarily due to the processor design and how it boots to have the flash start at address 0x00000000 so the first bank is from 0x00000000 to 0x00000ffff the second 0x00001000 to 0x00001fff, and so on. so the first level address decoder only needs to look at bits 31:28 in my design to see that this is for the flashes. then bits 13:12 are examined to determine which flash bank and then the transaction is enabled to the specific bank.
ram same deal say I implemented ram as two banks of 0x2000 bytes, starting at the processors address space 0x20000000, so examine bits 31:28 in the first decoder, enable this on the sram bus, examine bit 13 on the sram bus to determine which bank then send bits 12:0 to the specific sram to have it do its thing.
address space is arbitrary, someone decided how they wanted to divide it up, had some number of things they needed to fit into the space, ideally decode as few bits as possible at each layer to save logic and simply implement it.
How do these addresses get used plays into the memory mapped vs I/O mapped. So most of the flash access is instruction fetches, so those are not generated by instructions those are part of the processor logic, driven by the programmer that lays the tracks for the train to follow, sequential segments of code with occasional turns or forks. Lets assume that all flash is accessed that way, even though we know it is there in the address space and can be accessed in other ways not to mention it has to be written somehow. Then there is SRAM we use that to store bits, numbers, strings, pixels, whatever. That is generally accessed using load/store instructions or an overloaded mov instruction.
What intel did which wasnt unique to them you can look at the DEC PDPs and others, was to create an instruction that caused a different kind of access, in intels case the I/O port read/write simply created an additional address/control line. You can easily see on the 8088/86 that you had address and data and some control signals including an I/O signal. That was it memory mapped I/O vs I/O mapped I/O had to do with did you use the mov instruction to read/write or the I/O instructions to read write? then an address goes out data comes back but along with read/write control and that address there was an additional addres/control signal.
In my fictional MCU I could have bit 31 be the I/O bit 0x41100123 could be some perihperal register and 0xC1100123 could be something else.
The implementation at the time for I/O mapped I/O in these early intel systems is take the video card as a good example. The control registers that determine how many pixels wide, how many high, bits per pixel/video mode, etc were control and status registers and they implemented control and status as I/O looking for I/O bus transactions. But the pixel memory itself, the relatively large block of ram that holds the pixels was memory mapped. They basically for that example and others memory on the peripheral was mapped using read/write/mov based transactions and control and status, non memory, using I/O. Was an interesting idea that had a history (specific instructions in the instruction set to access the tty/uart rather than addresses in I/O space), but became an easy marketing/design target for motorola to beat up intel on briefly. (the reality is everyone uses segmentation/windowing in addressing, they just hide it) they could have and I think later with pci did make it so you can get to control and status through either, I can get to 123 main street by turning right off of 1st street or by turning left off of 2nd two paths to the same dwelling.