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I want to create a 16X1 mux with 4X1 mux.So can I create a module for 16x1 mux in this form? module 16X1 (OUT,I0[0:3],I1[0:3],I2[0:3],I3[0:3],S4,S3,S2,S1)

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  • \$\begingroup\$ I read the question wrong: Yes you can but nobody (outside education assignments for student) writes standalone muxes. You would normally use an if or case or even simpler use an index: assign i = vector[select]; \$\endgroup\$ – Oldfart Feb 27 '20 at 15:59
  • \$\begingroup\$ Yes,you are correct,I'm a student. \$\endgroup\$ – DragonikOverlord Mar 1 '20 at 2:33
  • \$\begingroup\$ Dataflow modelling hasn't been done yet. 16x1 mux was tedious to write so I thought maybe put the concept of arrays to use. Why do arrays have such limited use in verilog? \$\endgroup\$ – DragonikOverlord Mar 1 '20 at 2:45
  • \$\begingroup\$ "Why do arrays have such limited use in Verilog?" I suggest you post a question about that because a comment is too short for the answer. Before you do: think about this: Verilog is a HARDWARE description language. \$\endgroup\$ – Oldfart Mar 1 '20 at 7:34
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Yes you can as long as you use the I1[0:3], I2[0:3], I3[0:3], I4[0:3], in the correct order as will be specified or else you'll get wrong answer at the output.

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  • \$\begingroup\$ No,I just checked in EDA and verilog apparently doesn't support arrays in port declaration.Only System verilog allows arrays apparently. \$\endgroup\$ – DragonikOverlord Mar 1 '20 at 2:42

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