# Is it possible to take array inputs in module terminal list?

I want to create a 16X1 mux with 4X1 mux.So can I create a module for 16x1 mux in this form? module 16X1 (OUT,I0[0:3],I1[0:3],I2[0:3],I3[0:3],S4,S3,S2,S1)

• I read the question wrong: Yes you can but nobody (outside education assignments for student) writes standalone muxes. You would normally use an if or case or even simpler use an index: assign i = vector[select]; – Oldfart Feb 27 '20 at 15:59
• Yes,you are correct,I'm a student. – DragonikOverlord Mar 1 '20 at 2:33
• Dataflow modelling hasn't been done yet. 16x1 mux was tedious to write so I thought maybe put the concept of arrays to use. Why do arrays have such limited use in verilog? – DragonikOverlord Mar 1 '20 at 2:45
• "Why do arrays have such limited use in Verilog?" I suggest you post a question about that because a comment is too short for the answer. Before you do: think about this: Verilog is a HARDWARE description language. – Oldfart Mar 1 '20 at 7:34