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I have a 64-bit register that I would like to right shift n times, with 0<=n<=64, implemented as such

always_ff 
   data[63:0] <= (data >> n);

I was just wondering what this would result in during synthesis/implementation. In other words, what type of hardware would the compilers infer from this logic? In simulation, the block diagram was only showing >>, which wasn't very clear. Thanks.

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    \$\begingroup\$ Easy way to confirm the answers is, open the synthesis guide of whichever tool you are using (like Vivado or DC) and find the inference details of each Verilog constructs and operators. There are chances that some tool may not support some operators. So be careful. \$\endgroup\$
    – maximus
    Feb 28, 2020 at 10:53

2 Answers 2

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I don't know if there's a good solution beyond 64 63:1 multiplexers, each one of which is comprised of 21 4:1s or 63 2:1s, depending on the architecture. If delay time or gate count is a priority for you, you might want to generate something that would clock the register n times based on a trigger event.

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  • \$\begingroup\$ I don't think all that logic is necessary. For example, bit 63 of the output is either equal to data[63] (if n=0), or it's 0 (for any other n). Bit 62 of the output is only nonzero when n is 0 or 1. Etc. Of course the sysnthesis tool is likely to find this optimization on its own, even if you code 64 mux's. \$\endgroup\$
    – The Photon
    Feb 27, 2020 at 22:17
  • \$\begingroup\$ Assuming that any shift results in zero padding the right n bits, yes. In a practical device, there's got to be some way of reloading the register, or its usefulness won't last long. \$\endgroup\$ Feb 28, 2020 at 13:20
  • \$\begingroup\$ In Verilog the >> pads with 0's. If you want arithmetic shift, you need to use >>>. \$\endgroup\$
    – The Photon
    Feb 28, 2020 at 15:02
  • \$\begingroup\$ I was assuming that wasn't OP's entire design. Still going to be a lot of gates. \$\endgroup\$ Feb 28, 2020 at 15:18
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In general, the way that is implemented is with a series of muxes. One of them selects between the input data and the input data shifted by 1 bit, the next one shifts by 2 bits, the next one by 4, etc. The bits of n are then used as the select inputs for those muxes. Shifting by 64 bits requires 6 levels of 64 bit 2:1 muxes. These could possibly end up being packed 2 to a 6 input LUT, for 3 levels of logic, depending on what the tools do with it.

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