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It is my first time working on a 4-layer pcb design with PCIe golden finger. I have 2 voltage levels, 3.3V and 12V. I set the third layer to be the power plane. Does it mean that I have to always put my two power planes on this layer?

In my case, for 12V, all the connections can be done on the top layer. I am not sure whether I can just create a power plane 12V on the top layer. And if it is wrong, how can I make the connection between the top layer 12V connection with the third layer 12V power plane? It might seem a bit weird as I already make the connection on the top layer.

Thank you!

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You can put your power planes on whichever you like.

For a 4-layer board I usually don't bother assigning a specific layer for "power planes" - I the plane layers are usually primarily ground, to ensure unbroken planes under high frequency or analog signalling. Power planes then fit in and around as necessary, ensuring plenty of decoupling capacitors of course.


If the +12V can be routed nicely on the top layer and it saves vias to do so, you might as well route it there. Assuming your plane is large enough on a single layer to provide the current you require, there is no point also routing it on an inner layer as well.

There is usually an order of precedence for signals when routing PCBs, and this also includes power planes. As you mention PCIe, the most critical part to route is the SERDES traces which must have an unbroken ground plane directly beneath or above them (i.e. no signals or power planes cutting across through the ground underneath).

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  • \$\begingroup\$ Hi. Thanks for the reply. In terms of power plane, can I say that I should set the rest area on the third layer to be gnd? As I have tx and rx signals on top and bottom layers and my second layer is gnd, do I actually need to connect the bottom layer gnd signal with the third layer gnd plane? Thanks! \$\endgroup\$
    – Ruiying Wu
    Feb 28, 2020 at 18:16
  • \$\begingroup\$ @RuiyingWu As you have high speed lines on both sides, you'll need ground on both inner layers in regions below the high speed signals. I'd then run stitching vias down each side of the differential pairs to stitch the grounds together. \$\endgroup\$ Feb 28, 2020 at 18:38

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