There was an assignment as follows: implement a counter which gets as an input of 8 pulses, 5 volts each, with frequency of 40K Hz, without using counter block, or any IC components. In the output there are 8 diodes, with each pulse another diode should be activated, such that with the first pulse - the first diode get's activated, with the second pulse, the second diode get's activated, and so on.

my idea of implementation was to use FF's to act as a shift register - on the first pulse, the first FF passes the 5 volt and lights up the first diode, on the second pulse, the second FF get's activated and lights up the second diode, and so on.

I tried to implement a FF of my own, using logic gates, but for some reason, it doesn't work. When I tried using the FF component which multisim offers, I linked the FF's in a row, but the second FF get's contaminated too soon, before the second pulse arrives - thus activating the diode before the time. perhaps anyone could give me some advice on what am i doing wrong:

  1. what's the problem with the way I connected the FF's in the first picture?

  2. why does the logic gate implementation of my FF doesn't work?

Full design:

enter image description here

the simulation result of the blue point X marked in picture (1) - the AND gate output:

enter image description here

mulation result of the FF's as depicted in picture (1):

enter image description here

NOTE: the second pulse arrives after 2.5x(10^-5) sec, but the second FF (depicted in green in the 3rd picture) gets contaminated and activates the diode after 2x(10^-9) sec

and last, my FF implementation using logic gates which refuses to work and outputs zero all the time:

enter image description here

Thank you very much for you time and attention!

  • \$\begingroup\$ Why have you got IBH62 diodes connecting the outputs to ground. This doesn't make sense. Also the IBH62 is "what" type of diode. Couldn't find a data sheet. \$\endgroup\$
    – Andy aka
    Feb 28 '20 at 10:34

First circuit using FFs looks strange:

  • !CLR pins of the FFs are on the ground, thus both of them must be in state 0;
  • second FF, when first goes 0, will have its !PR input also in low state, and this is race condition for the reset state and the FF's state will be undefined;
  • why D1 is connected to !Q of first FF and D2 is connected to Q of second FF?

There're a lot of "shift register circuit" circuits on the internet, reuse their design instead of inventing the bycicle.

Regarding your gated circuit: I suspect you must add propagation delays to the components for simulation to take place properly. In ideal conditions, when each gate propagates the signal immediately, the device will not work.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.