Both are the same electrically, but B is more compact and most people will find it easier to understand. If you want to emphasize that each cap is associated with a specific ground/power pair, you can use A to indicate that, especially if a different person is doing the layout.
As a professional electronics engineer I've never ever seen A. B is definitly the way to go. If the layout will be done by someone else you can always add a remark. But a layouter that doesnt know he should place bypass caps close to each pin shouldnt be a layouter at all.
B for sure in this case, with a separate doc for the placement (or even a diagram copy-pasted into the schematic.) For a big SoC it’s really the only way to represent the mixed values designers sometimes use to get good low-to-high frequency coverage.
The A drawing obscures the intent and is harder to read. The cap lines don’t even land on chip pin pairs. If I had to work with it I’d redraw it; it’s that bad.
That said, I’ve done style A on smaller ICs with individual caps on sensitive paired pins (PHY power and such), where having a small loop area is critical.
30 years of Electronic design.
I understand what you are doing with A referencing each cap to a set of pins possibly to assist when doing pcb layout to keep track of the caps for pcb placement to pins.
B is cleaner but provides no direct assignment to which pins. However Does it really matter??
If you work at a company they may offer their standards of how they like schematics done. I would recommend you ask.
If this is your own project and you are the boss.... Do what makes sense to you. However if you are the boss and interface your schematics to others easy reading schematics that provide accurate efficient clear information will save time and money.
You will also understand that many people will offer their opinion and some with a very strong opinion.
In general... Schematics should be easy to follow providing ease access to accurate efficient clear information.
With experience you will understand. Happy designing.
I suggest B. A rule I've found good to abide by when drawing a schematic is not to place any 4 way ties. So never have a node that splits in all 4 directions. The reason for this is to easily be able to point out an accidental connection between two crossing nets. It's useful for design review because if you see a 4 way tie in someone's schematic you can easily call it as a connection that should not be there. But with that, I agree what @Hasan said where I think the most important thing to do may be what those around you agree to be standard. They'll be the ones reading the schematic and therefore the ones that really need to understand it. So in your case again B, since others are suggesting it to you
The way the schematic is drawn implies that capacitors should be tied between particular pairs of pins, but I don't think the pairs shown are what is intended (e.g. it looks like G5 connects to Y8 and G3 to Y6). If I wanted to show cap placement on the schematic, I would use a draw symbol where the power and ground for each pair were placed adjacent (meaning power and ground connections would alternate), and then I would place a cap near each pair and extend the wires to vertical power/ground buses.
If it's important that the chip's connections to each cap be better than its connection to the bus, I might use a schematic symbol that looks like a short wire with dots at the end, and put that between the each cap and the power/ground bus. The footprint for the symbol should be two tiny pads if necessary for a design rule check, but there should be a connection between them for final rendering (the purpose of the symbol would be to make the connection between each chip and its cap be a separate net from power/ground during layout, but the nets should be merged after the layout is complete).
Electrically they are the same, as long as we speak schematic only. When it comes to layout, that's a different story, as each of the connections (wires) will be traces and each of them are linked to certain parasitic components (e.g. inductances) depending on how you design the circuit board. In the schematic it's typically all about readability and my best guess would be, that most engineers would have an easier time, to figure out what's going on in drawing B.
As far as your PCB design tool is concerned your schematic is crunched-down to a list of components and a list of nets that are imported into the PCB editor, but a list of components and a netlist is far from a complete specification of a design. In particular in the real-world tracks have resistance and inductance, so simply saying a capacitor should be connected to a power net and the ground net does not give us sufficient information to correctly place said capacitor.
A schematic also provides information for humans which may go beyond what can be represented in the net-list, how far to go beyond providing a "graphical representation of a component list and net-list" is something of a matter of style. It is likely that a practical schematic will always be an incomplete specification of a design.
The question then is how much information to include about decoupling capacitors, some designers just put all the decoupling capacitors for a rail together, giving no indication of what chip they go with. I personally find that unhelpful, IMO it is useful to maintain an association between a major component and it's support components (not least because I will sometimes want to copy/paste parts of a design).
At the other extreme you can try to indicate which capacitor goes with which power pin, but there are a couple of problems with this, firstly it tends to blow up schematic size a lot, secondly especially with BGAs, it won't be a case of one capacitor per power pin because there simply is not enough room for that.
So many designers end up in a middle-ground, grouping the decoupling capactitors with their associated IC, but not indicating which pin each capacitor goes with. This is the style depicted in your example "B".
Whatever your strategy, if you are going to include additional information in the schematic beyond what is visible in the net list you should bloody well make sure that information is actually accurate. Your schematic "A" implies to me that C124 is associated with power pin G5 and ground pin V8 which seems unlikely.
I think you are trying to increase the capacity of a capacitor. If the purpose is only that then the length of the PCB track plays a significant role. Voltage drop across the track is different for each capacitor so that the energy stored in the each capacitor will be different. I suggest go with B.