On various technology (discrete, ASIC, FPGA), I'd like to know if the asynchronous signals set and reset are always present on D (edge-triggered) flip-flops. If not how the reset process can be handled ?


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I believe FPGAs always have an asynchronous reset for the whole device, as part of the programming process. I don't know whether you can always wire individual async resets to individual cells.

In ASIC technology, the cell libraries have the option of flops with and without asynchronous reset. Which one gets used depends on what you asked for in Verilog. If you didn't design in a reset, you don't get one.

You could have a synchronous reset instead: Reset: synchronous vs asynchronous

By "discrete", do you mean 74-series style individual devices?

  • \$\begingroup\$ Recent FPGAs (like for the last 10 years or more) from the major vendors offer a choice of asynchronous or synchronous reset or clear on every flip-flop. Usually the power up state must be chosen to correspond to whether you use the reset or clear function. \$\endgroup\$
    – The Photon
    Nov 7, 2012 at 16:51
  • \$\begingroup\$ yes, discrete means individal devices, for me \$\endgroup\$
    – JCLL
    Nov 11, 2012 at 20:28

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