I'm struggling to wrap my mind behind the concept of RS flip-flop. For me, the diagram seems very non-intuitive. Whenever I accept, for example, that Q is HIGH and follow signal route (is it even correct to say so?) I come to a logical contradiction (say, NOT Q being also HIGH). Could you please share some knowledge and enlighten me?
I think that your confusion comes from treating the output identifiers Q and /Q literally.
As Curd says, if both S and R are held high (in Oli's diagram), both Q and /Q will be simultaneously low. So from a purely logical perspective, the assumption that the outputs are Q and /Q must be wrong.
It is better to label the outputs of two-gate SR latches as Q and Q', with Q' = /Q except when S = R = 1.
Lets have a look at the NOR gate version of the SR Latch:
If we start with S and R inputs low and Q high, then the bottom gate has a logic high at it's input. This means it's output Qbar is low. Since the top gate has both inputs low, it's output is high and there is no conflict.
Now if we bring R high, Q must go low. Now the bottom gate has both inputs low so it's output Qbar must go high. If we let R go low again things stay as they are because Qbar is now high and holding the top gates other input high.
In the animation above red is 1 and black is 0.
If you look at it long enough it will make sense.
To clarify things a little more, here is the truth table for the above latch:
Note that both inputs high is not allowed, as it violates the Q != Qbar as discussed in the other answers.