4
\$\begingroup\$

I'm struggling to wrap my mind behind the concept of RS flip-flop. For me, the diagram seems very non-intuitive. Whenever I accept, for example, that Q is HIGH and follow signal route (is it even correct to say so?) I come to a logical contradiction (say, NOT Q being also HIGH). Could you please share some knowledge and enlighten me?

\$\endgroup\$
  • \$\begingroup\$ Adding a diagram makes it easier for people to help you, even if it is a commonly known circuit. \$\endgroup\$ – Trygve Laugstøl Nov 7 '12 at 15:56
4
\$\begingroup\$

I think that your confusion comes from treating the output identifiers Q and /Q literally.

As Curd says, if both S and R are held high (in Oli's diagram), both Q and /Q will be simultaneously low. So from a purely logical perspective, the assumption that the outputs are Q and /Q must be wrong.

It is better to label the outputs of two-gate SR latches as Q and Q', with Q' = /Q except when S = R = 1.

\$\endgroup\$
6
\$\begingroup\$

Lets have a look at the NOR gate version of the SR Latch:

SR Latch

If we start with S and R inputs low and Q high, then the bottom gate has a logic high at it's input. This means it's output Qbar is low. Since the top gate has both inputs low, it's output is high and there is no conflict.

Now if we bring R high, Q must go low. Now the bottom gate has both inputs low so it's output Qbar must go high. If we let R go low again things stay as they are because Qbar is now high and holding the top gates other input high.

In the animation above red is 1 and black is 0.

If you look at it long enough it will make sense.

To clarify things a little more, here is the truth table for the above latch:

SR Truth Table

Note that both inputs high is not allowed, as it violates the Q != Qbar as discussed in the other answers.

Wiki page on Flip Flops

\$\endgroup\$
  • \$\begingroup\$ Would the case with NAND be any different? \$\endgroup\$ – Vladislavs Burakovs Nov 7 '12 at 12:32
  • 1
    \$\begingroup\$ The cross coupled SR flip-flop built of two NAND gates will work similar except the pulses applied to the inputs to SET or RESET the flip-flop would be low level and the inactive state of these inputs would be sitting at a high level. \$\endgroup\$ – Michael Karas Nov 7 '12 at 12:58
3
\$\begingroup\$

With a NAND-Flip-Flop it is not a contradiction to have both Q and ~Q high.
This is the case when both inputs ~S and ~R are low, i.e. active.

You get the analog case with a NOR-Flip-Flop with both inputs S and R high.
Then both outputs Q and ~Q will be low.

\$\endgroup\$
  • \$\begingroup\$ But isn't this basic logic, that Q must be the opposite of ~Q by definition ? \$\endgroup\$ – Vladislavs Burakovs Nov 7 '12 at 14:45
  • \$\begingroup\$ Under normal conditions, yes. Normal conditions means only one of Set or Reset is active. If you have both active then the logic breaks down. This is not a problem, though, because it is designed to function this way and the rules stipulate that only one input must be active. \$\endgroup\$ – akohlsmith Nov 7 '12 at 14:47
  • \$\begingroup\$ @Владислав Бураков: You are right; but this is rather an error of a suboptimal notation (though it is the common notation) than of logic. \$\endgroup\$ – Curd Nov 7 '12 at 23:28

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.