I've read that increasing the doping concentration would cause the carrier mobility to decrease, but at the same time, it would lower the threshold voltage. So a few questions come to mind:

  1. When we're talking about doping concentration, say of a PMOS, are we talking about the heavily doped (with p-type impurity) region of drain and source or n-substrate? I'm assuming it's the former since that's what creates the channel.

  2. Which is more dominant in terms of drain current change - the decrease in carrier mobility or the lowered threshold voltage? I suppose we can use the I-V equation in triode region, i.e. a decrease in carrier mobility lowers the current (i.e. lower switching speed) and a decrease in threshold voltage increases the current (i.e. higher switching speed).

  3. When the threshold voltage is lowered, overdrive voltage (Vov) goes up, would this also mean the supply voltage (Vsd) need to be higher for the MOS to go to saturation? When we talk about supply voltage is it Vsd or the gate voltage?

I feel like I have an idea but am not understanding this clearly. Thanks.


If I recall rightly, the triode-mode drain current in a long channel ( > 1 micron length) FET is

Id = K/2 * W/L * (Vgs - Vt)^2

where K is Mu * Cox

and where MU is the mobility.

  • 1
    \$\begingroup\$ I thought that's the equation for saturation region? \$\endgroup\$ Mar 8 '20 at 19:20
  • \$\begingroup\$ This answer is basically wrong.Delete it as fast as you can \$\endgroup\$
    – Miss Mulan
    Aug 4 '21 at 2:41

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