# How does ESD protection work with TVS diodes?

I have two questions regarding TVS diodes.

This paper describes very well what happens when you want to protect a circuit with a unidirectional and bidirectional TVS diode and a positive and negative ESD happen:

http://www.protekdevices.com/xyz/documents/kb/tech/ta1003.pdf

Now let's consider this situation:

If an +8 kV ESD happens, then D2 will be forward biased and conduct, and D1 will be reversed biased and conducting as well. Where will the current due to the ESD go through? Is there a predominant diode? For an instant there is a connection between VCC and GND, isn't it a problem?

Second question: let's say I need to protect a pin so that its voltage range stays between 2 and 4 V. Will this below circuit, where the diodes have a reverse voltage of 4 V, work?

• D1 is reverse biased hence..... it (will/won't) conduct? Commented Mar 1, 2020 at 15:06
• Well if D1 is reverse biased and that voltage is above the reverse breakdown voltage, then it would conduct. Am I right ?
– user244024
Commented Mar 1, 2020 at 15:13
• How can it rise above 6 or 7 volts ? Commented Mar 1, 2020 at 15:15
• Because of positive or negative ESD, which can be for example +- 8 kV
– user244024
Commented Mar 1, 2020 at 15:37

You are mixing up two ESD solutions and mashing them together: Rail clamp diodes and TVS didoes.

If you are using rail clamp diodes, then you do this:

simulate this circuit – Schematic created using CircuitLab

• The rail clamp diodes ONLY clamp line voltages in forward bias.
• The line voltage is kept between $$\ V_{dd} + |V_f| > V_{line} > GND-|V_f|\$$
• Rail clamp diodes require the power supply to be present in order to provide protection.
• $$\V_r\$$ >> $$\V_f\$$ so one of the diodes will conduct in forward bias which prevents the line voltage from getting high enough to cause reverse breakdown in the other diode. Therefore, only one diode ever conducts. You cannot have both conducting so no short-circuit.

If you use TVS diodes then you do this:

simulate this circuit

• The unidirectional TVS diode clamps positive spikes in reverse breakdown and clamps negative spikes in forward bias.
• The line voltage is kept between $$\ |V_r| > V_{line} > GND-|V_f|\$$
• TVS diodes do not requires the power supply to be present in order to provide protection.

If you use bi-directional TVS diodes, then you do this:

simulate this circuit

• The bidirectional TVS only ever clamps the line voltage by one internal unidirectional TVS diode breaking down in reverse while the other is forward biased.
• It keeps the line voltage between $$\+|V_r+V_f| > V_{line} > -|V_r+V_f|\$$
• It does not requires the power supply to be present to provide protection.

• More precise voltage clamp thresholds
• Dissipates less heat in the diode than the TVS diode (since it clamps with $$\V_{f}\$$ and $$\|V_{f}| < |V_{r}|\$$)
• Instead, most of the spike's power is dumped into the supply which means a more powerful spike can be handled as long as the power supply can handle it

• Needs the power supply to be on to provide protection

• Protects even with no power supply

• All the power in the spike is dissipated as heat in the TVS diode (this is what lets it protect even when no power supply is present) which limits how powerful of a spike can be handled. This can make TVS diodes big which makes them expensive.

All that said, if you actually wanted to mash rail clamp and TVS diodes together, you would use the rail clamp diodes but have the bottom diode, D2, be a unidirectional TVS diode. With no power, it works like the unidirectional diode circuit. With power, it works like the rail clamp diode circuit (as long as $$\|V_{r.TVS}| > Vdd + |V_{f.D1}|\$$). If it was not, then the TVS would breakdown in reverse before D1 became forward biased.

simulate this circuit

• OK thanks it's more clear now. In the first solution, if there is a positive ESD, then D2 would be reverse biased with a very high voltage. In that case, D2 would burn, right ? So the second solution is better ? With both solution, a negative ESD would introduce a small negative voltage on the pin that needs to be protected. That's why I was wondering if there was a solution to ensure that the voltage stays in a positive interval.
– user244024
Commented Mar 1, 2020 at 19:13
• @innu3nd0 No. Remember that D1 is there and that Vr >> Vf. So as long as the diodes are faster than the spike, D1 will forward bias during a forward spike which prevents the line voltage from getting high enough to reverse bias D2. Commented Mar 1, 2020 at 19:14
• @innu3nd0 Neither solution is really objectively better. It depends what you want. The TVS diode solution still provides protection when no power supply is present. However, the rail clamp diodes provide more precise thresholds for voltage clamping clamping since it is determined by Vf and the rail supply voltage. If you look at TVS diode Vr vs current curves, it is not very precise and the voltage drop across the TVS diode can increase quite a bit as more current flows through it. This makes the voltage clamping threshold vary. Commented Mar 1, 2020 at 19:16
• @innu3nd0 All the heat is dissipated in the TVS diode (this is what lets it provide protection even with no power supply). But that means that it is more limited in power handling since the rail clamp diodes dissipate less heat due to lower voltage drop and instead dump all the power into the supply. Commented Mar 1, 2020 at 19:19
• Rail clamp diodes can work even when power is turned off. The rail clamp diodes feed the energy from the ESD pulse into the primary storage capacitor. As long as the capacitor has enough capacity that the energy from the pulse does not cause the voltage to raise above nominal level, the ESD is fully mitigated. You still have a point if a device has no big storage/reservoir capacitor built-in, and the power supply with a suitable cap is not connected to the device at the moment. Commented Mar 2, 2020 at 0:18

If you consider what the 8 kV ESD really is in terms of energy storage devices and resistors it'll look something like this: -

Picture from here.

The 150 pF capacitor is charged to +8,000 volts but, your target circuit doesn't actually receive that voltage directly; there is a 330 ohm resistor in the way. That means the peak current delivered can be up to 24.24 amps.

So, when that hits the circuit node called "pin 1", D2 is forward biased and takes the brunt of the 24 amp spike and passes it through to the 6 volt DC bus. If the capacitance on your DC bus is (say) 100 uF, the voltage starts rising at this rate: -

$$I = C\dfrac{dV}{dt}\Longrightarrow \dfrac{dV}{dt} = \dfrac{24.24\text{ A}}{100\text{ uF}} = 242,240 \text{ volts/sec}$$

But, the CR time for the pulse is only 330 x 150 E-12 = 50 ns and so, the voltage might rise only 12 mV in those 50 ns. Taking this to extremes you couldn't really see the voltage rising much more than 0.1 volts before the ESD pulse has evaporated to nothing.

But how much voltage does the diode drop when taking 24 amps? It'll be 1 or 2 volts depending on the diode so, the maximum voltage that might be seen on pin 1 could be as high as 8.1 volts AND D1 (the other diode) will remain reverse biased with no harm.

Of course, 8.1 volts might still do serious harm to your pin so, most folk would have a 1 kohm resistor to the outside world from where your diodes are (see R1 below). This then restricts the current to 8000/1330 amps = 6 amps. The knock on effect should be clear.

Even so, it doesn't guarantee the avoidance of circuit failure and, in addition to the 1 kohm mentioned above, another 1 kohm resistor is placed directly in series with the input pin. The 2nd resistor (R2) makes use of the chip's data sheet that would inform you what the maximum current is that could be injected without harm.

The ESD discharge can also be negative, in which case D1 takes the brunt of the current and passes it (more safely) to ground.

Also, if pin 1 is an output, you might not be able to live with a couple of kohm of extra resistors and different measures have to be taken.

• Thank for the detailed answer. Could you explain how the CR time for the pulse is derived as 330 x 150 E-12 = 50 ns? Shouldn't it be 330x100E-6 = 33 msec ?
– Geo
Commented Nov 23, 2020 at 4:09
• @George the 100 uF is in series with the 150 pF and the 150 pF dominates the C part of the CR time. Add up 100 uF and 150 pF when in series and what do you get. Commented Nov 23, 2020 at 9:01