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I'm fairly new to embedded developping and I'm trying to read and write to a 1-wire device (DS18B20) using USART. After digging around I found two alternatives:

  1. Connecting USART RX and TX pins with MOSFETS and resistors (which to me is a bit complicated)

enter image description here

  1. Using USART's single wire half duplex mode.

My Question is: I wanted to know if single wire mode does this internally or do I still have to do it.

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    \$\begingroup\$ "some kind of hardware connections": it's absolutely not clear what you mean. I don't think we can help you until you add a full schematic to your question, describing what you've designed so far. \$\endgroup\$ – Marcus Müller Mar 2 '20 at 9:10
  • \$\begingroup\$ single wire half duplex mode..can you share the reference? \$\endgroup\$ – User323693 Mar 2 '20 at 9:17
  • \$\begingroup\$ @MarcusMüller I didnt design anything. The schematic I just added is the hardware connection needed to communicate with USART in asynchronous mode. I wanted to know if single wire mode does this internally or do I still have to do it. \$\endgroup\$ – DTl Mar 2 '20 at 9:19
  • \$\begingroup\$ @User323693 What do you mean by reference ? \$\endgroup\$ – DTl Mar 2 '20 at 9:20
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    \$\begingroup\$ @DTl that schematic helps a lot; before, we had no idea what you were referring to. \$\endgroup\$ – Marcus Müller Mar 2 '20 at 9:24
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Short answer:

you don't need external circuitry if you enable open drain mode for the UART Tx pin when configured as single wire mode. Check in detail with your actual MCU.


Referring to the application note from maxim:

enter image description here

From the same Note:

Since most UART transmit data (TXD) pins are not open drain, an external open-drain buffer circuit is usually needed. This circuit can be constructed out of discrete components as shown in Figure 2a, or integrated solutions such as the Fairchild NC7WZ07 shown in Figure 2b are available. In both circuits, the 4.7kΩ pullup resistor provides the logic high on the 1-Wire bus.

From STM32 document:

enter image description here

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Yes, 1-wire is an open drain idle-pullup bus, and you, as single device, will need to implement that element you show.

The "true" 1-wire devices like your DS... IC have that built-in.

Note that this doesn't solve the issues of adhering to 1-wire bus timings, but that's a microcontroller software issue.

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  • \$\begingroup\$ I'm sorry I didnt get what you mean. So by using USART single wire mode, I dont have to do that schematic ? \$\endgroup\$ – DTl Mar 2 '20 at 9:30
  • \$\begingroup\$ you have to, as I said: "need to have that element". Let me ever so slightly rephrase. \$\endgroup\$ – Marcus Müller Mar 2 '20 at 9:31
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schematic

simulate this circuit – Schematic created using CircuitLab

STM32, as from User323693 previous answer, has a "Single Wire" mode very close to what "onewire" require for. Caveat about is we require a simultaneous receive and transmit to implement OW over Usart. ST provide HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_EnableReceiver() this way receiver is off when transmit and viceversa. Hacking Hal library I produced a full duplex mode Single Wire Library, actual preview code is here: Single wire Access Onewire on STM32. Inspired from this post I plan complete code and get published in a short time


Edit: march 23 code was published on GitHub, HAL version was buggy so I released a new LL based one has no issue on IRQ. LL version tested over STM32F030 (release), F401, F303RETX, (both HAL and LL), G071.

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  • \$\begingroup\$ Welcome to EE.SE. Note that "previous answer" can be hard to follow as posts move up and down by votes and user sorting preferences. \$\endgroup\$ – Transistor Mar 21 '20 at 13:08
  • \$\begingroup\$ That would be helpful ! Thank you \$\endgroup\$ – DTl Mar 21 '20 at 16:36
  • \$\begingroup\$ March 23 code is online on GitHub: F030 Branch, zipfile has complete project code and setting. Picture illustrate setup, schematics and some issue catch by Salea Logic 8. Please check todolist and leave me some time to learn about GitHub \$\endgroup\$ – roberto romano Mar 23 '20 at 18:36

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