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I have read about the internal structure of SRAM and we need 6 transistors to store 1 bit.

But what bothers me is why can't it be made using D-flip flops instead of going deep to transistor-level. It will lead to the same result, so where is the riddle?

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    \$\begingroup\$ Because D flip flops have more transistors? You are aware that logic gates, latches, and flip flops are comprised of transistors, right? They don't work off magic 0s and 1s. \$\endgroup\$
    – user103380
    Commented Mar 2, 2020 at 17:15
  • \$\begingroup\$ SRAM, flip flops, logic gates, muxes, look-up tables, etc. are all just different configurations of transistors. \$\endgroup\$
    – DKNguyen
    Commented Mar 2, 2020 at 17:21
  • \$\begingroup\$ If I remember a D-FF has about 12 transistors but then you have only the storage part. The data multiplexing is still missing .The 6 transistors of the SRAM bit also include the multiplexing. \$\endgroup\$
    – Oldfart
    Commented Mar 2, 2020 at 17:26

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The most common form of DFF uses six 3-input basic gates (NAND or NOR). In CMOS, a 3-input gate requires 6 transistors, so the total for the DFF would be about 36 transistors.

In an SRAM cell, four of the transistors do the actual data storage, while the other two connect the storage cell to the bit lines under control of the word line. The DFF would require at least one more transistor to accomplish the latter function.

A simpler (not edge-triggered) D latch would still require four 2-input gates, or at least 16 transistors.

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  • \$\begingroup\$ In CMOS, a DFF is made from transmission gates and inverters. An edge-triggered FF is 18 transistors, while a level-sensitive latch is 8 transistors. \$\endgroup\$
    – Elliot Alderson
    Commented Mar 2, 2020 at 22:53

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