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I've looked at some other forums and know that this type of error occurs when multiple outputs drive the same input however I am struggling to see how to fix this error and what specifically is causing it within my code. For context, the code that I am attaching is a submodule that is instantiated in a top traffic light controller module. The purpose of this module is to control what state the traffic light controller is in (Green_red, yellow_red, red_green, and red_yellow). The code that I wrote works when I simulate it with a testbench, however, I keep getting the same errors. There are two other submodules that have the same errors that I didn't attach, however, they follow the same exact logic as the car module just for the different inputs.

This is my code for the top module:

module Controller (clk, rst, c, e, p, SCL, SVL, current);
    input  clk, rst, c, e, p; //Clock, reset, and sensors
    output reg [2:0] SCL, SVL; //Lights for Santa Clara and Seventh. 100 is green, 010 is yellow, and 001 is red
    output reg [1:0] current; //Current state

wire [1:0] c_current, e_current, p_current;
wire c_served, e_served, p_served;
wire c_begin, e_begin, p_begin; 

wire [2:0] f_reset; //Forced reset for when multiple sensors are detected at same time. 100 is for car, 010 is for emg, 001 is for ped
reg [2:0] forced;

assign f_reset = forced;

parameter SCG_SVR = 2'b00, // Santa Clara green, Seventh red
          SCY_SVR = 2'b01, // Santa Clara yellow, Seventh red
          SCR_SVG = 2'b10, // Santa Clara red, Seventh green
          SCR_SVY = 2'b11; // Santa Clara red, Seventh yellow

initial //Default conditions
    begin
        current = SCG_SVR; 
        SCL = 3'b100;
        SVL = 3'b011;
    end

Car carl (clk, rst, c, c_begin, c_served, c_current, f_reset);
Emergency emg1 (clk, rst, e, e_begin, e_served, e_current, f_reset);
Pedestrian ped1 (clk, rst, p, p_begin, p_served, p_current, f_reset);

always @(posedge clk)
begin
    if (c_begin && ~e_begin) //Car has 2nd priority, occurs whenever emergency is not detected
        begin
            current = c_current;
            forced = 3'b011;
        end
    else if (p_begin && ~e_begin && ~c_begin) //Pedestrian has least priority, occurs whenever emergency and car aren't detected
        begin
            current = p_current;
            forced = 3'b110;
        end    
    else if (e_begin) //Emergency has the most priority
        begin
            current = e_current;
            forced = 3'b101;
        end
    else
        begin
            current = SCG_SVR; //Current state whenever nothing is detected
            forced = 3'b111;
        end
end

always @(posedge clk)
begin
    if (c_served || e_served || p_served) forced = 3'b000;
end

always @(posedge clk)
begin
    case(current)
        SCG_SVR: 
            begin
                SCL = 3'b100; //Santa Clara green
                SVL = 3'b001; //Seventh red
            end        
        SCY_SVR: 
            begin
                SCL = 3'b010; //Santa Clara yellow
                SVL = 3'b001; //Seventh red
            end        
        SCR_SVG: 
            begin
                SCL = 3'b001; //Santa Clara red
                SVL = 3'b100; //Seventh green
            end        
        SCR_SVY: 
            begin
                SCL = 3'b001; //Santa Clara red
                SVL = 3'b010; //Seventh yellow
            end
    endcase
end

endmodule

This is my code for the sub module:

module Car (clk, rst, c_reqd, c_beg, c_srvd, current_state, f_reset);
    input clk, rst, c_reqd; //Clock, reset, car requested
    input wire [2:0] f_reset;
    output reg c_srvd = 0, c_beg = 0; //Car served, car began
    output reg [1:0] current_state;

reg [1:0] next_state;

assign forced = f_reset;

parameter SCG_SVR = 2'b00, // Santa Clara green, Seventh red
          SCY_SVR = 2'b01, // Santa Clara yellow, Seventh red
          SCR_SVG = 2'b10, // Santa Clara red, Seventh green
          SCR_SVY = 2'b11; // Santa Clara red, Seventh yellow

integer counter = 0;

initial //Default condition
    begin
        next_state = SCG_SVR;        
    end

always @(*)
begin: CFSM_seq
    if (rst || f_reset[2] == 1)
        begin
            next_state = SCG_SVR;
            counter = 0;
        end
    else current_state = next_state;
end

always @ (posedge clk)
begin: CFSM_comb
    case(current_state)
        SCG_SVR:
            begin
                if (c_reqd)
                    begin
                        next_state = SCY_SVR;
                        c_srvd = 0;
                        c_beg = 1;
                    end
                else
                    begin
                        next_state = SCG_SVR;
                        c_srvd = 0;
                        c_beg = 0;
                    end                     
            end
        SCY_SVR:
            begin
                if (counter < 4)
                    begin
                        next_state = SCY_SVR;
                        counter = counter + 1;
                    end
                else
                    begin
                        next_state = SCR_SVG;
                        counter = 0;
                    end
            end            
        SCR_SVG:
            begin
                if (counter < 10)
                    begin
                        next_state = SCR_SVG;
                        counter = counter + 1;
                    end
                else
                    begin
                        next_state = SCR_SVY;
                        counter = 0;
                    end
            end        
        SCR_SVY:
            begin
                if (counter < 3)
                    begin
                        next_state = SCR_SVY;
                        counter = counter + 1;
                        if (counter == 1)
                            begin
                                c_srvd = 1;
                            end
                    end
                else
                    begin
                        next_state = SCG_SVR;
                        counter = 0;
                    end
            end        
    endcase                                                                    
end

endmodule

And these are some of the errors I'm getting:

[Synth 8-6859] multi-driven net on pin carl/next_state[1] with 1st driver pin 'carl/next_state_reg[1]__0/Q' 
[Synth 8-6859] multi-driven net on pin carl/next_state[1] with 2nd driver pin 'carl/next_state_reg[1]/Q' 
[Synth 8-6859] multi-driven net on pin carl/next_state[0] with 1st driver pin 'carl/next_state_reg[0]__0/Q' 
[Synth 8-6859] multi-driven net on pin carl/next_state[0] with 2nd driver pin 'carl/next_state_reg[0]/Q' 
[Synth 8-6859] multi-driven net on pin carl/counter[31] with 1st driver pin 'carl/counter_reg[31]__0/Q' 
[Synth 8-6859] multi-driven net on pin carl/counter[31] with 2nd driver pin 'carl/counter_reg[31]/Q' 
[Synth 8-6859] multi-driven net on pin carl/counter[30] with 1st driver pin 'carl/counter_reg[30]__0/Q' 
[Synth 8-6859] multi-driven net on pin carl/counter[30] with 2nd driver pin 'carl/counter_reg[30]/Q' 

//multiple more of the same errors with car1 and counter[n]
```
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  • 1
    \$\begingroup\$ You modify (drive) counter in both always constructs. \$\endgroup\$
    – Anonymous
    Mar 4, 2020 at 18:41

2 Answers 2

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You modify (drive) counter in both always constructs. It seems that first, small always is reset condition trigger, use async reset instead in the second construct, like this (as an example):

wire rst_n = ~(rst || (f_reset[2] == 1));

always @ (posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        counter = 0;
    end else begin
         ...
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You set forced, counter, and next_state from two different always blocks. Combine that into one block and it should work.

And you don't need a state where both lights are red at the same time?

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  • \$\begingroup\$ Alas, in the olden days we didn't need to have red in both directions. But you are right, it would greatly reduce the carnage at rush hour. \$\endgroup\$ Mar 4, 2020 at 22:55

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