Suppose that I am working with an FPGA and I synthesize two architectures A and B. A achieves a maximum frequency of 60 MHz on FPGA and B achieves 50 MHz on the same FPGA. Now suppose that I synthesize A for a different technology (a standard cell for instance) and on this new technology A achieves a frequency 10x higher of 600MHz. If now I synthesize B to the new technology, can I also expect a frequency 10x higher for B (500 MHz)?

I am aware that there are many factors and tolerances involved, but in general can we expect the same order of magnitude for both architectures? Or is it possible that A achieves 600 MHz and B only 150 MHz, for instance?

EDIT: thank you all for your answers and comments. I understand everything you wrote and most probably the problem is with me that, as a non-native speaker, have trouble to go straight to the point.

I am aware that there are many factors to be considered as I posted on my original question. I am aware of: number of layers of a technology such as 3 metal layers, 5 metal layers, 9 metal layers and so on; LUTs vs transistors, routing algorithm used, fan-out, voltage etc etc. The list is long and each one of these details have impact on the frequency of an architecture.

What I wanted to know in fact is if there are physical properties that inherently avoids frequency scaling no matter how much effort one puts on the details mentioned above. My background is that I never had access to tools such as the ones from Cadence or Synopsys to do a full custom synthesis going from verilog to GDSII. I only have access to FPGA tools and I am well aware that they are beast of completely different nature.

My real question was (and that I tried to wrote as concise as I could but that clearly I failed): are there any physical properties that no much how effort one puts on the details the frequency will be limited. Please consider my lack of practical experience on the subject so I'll just make up a non-realistic example: design A has 7-stage pipeline and B has a 5-stage pipeline and according to law/theorem/corollary/whatever that states that provides a maximum theoretical limit that a five stage pipeline design increases X fold times while a design with seven stage pipeline increases with X^1.3 fold times so no matter how much one put effort on details of architecture B, there's a theoretical limit that prevents B from achieving the same order of magnitude frequency of architecture A. Is there something like this? Or would it be the case that: no, there are no such theoretical limits, everything is dependent just on the details such as routing, placement and so on.

Because if I go down to the details, it is almost obvious that there will be differences, one technology may provide better routing than the other that gives A an advantage over B (or vice-versa) for example.

And to explain my background: I am a student that work with the design of microprocessor's micro-architectures. I have implemented architecture A with a 7-stage pipeline. B only has 2-stage pipeline but when synthesized A achieved 60 MHz while B achieved 50 MHz. For me this difference was small, negligible. I expected B to have a much lower frequency than A since it uses fewer pipeline stages. It goes against what the book says that larger pipelines allows for higher frequency (and here I am aware that a 7-stage pipeline can be considered to be a small one, that there would be necessary many more stages to be considered a long pipeline, it is just an example). Then I started to think: maybe its because it is FPGA technology and as frequencies are low there isn't so much difference, but maybe on higher speed technologies this difference would increase showing the clear advantage of a longer pipeline. Or would be the case that A and B grow similar regarding frequency? I really don't know because I don't have experience with synthesis with full custom, standard cells and so on.

A is a 7-stage pipeline that executes 4 instruction in parallel and runs at 60 MHz. B is 2-stage pipeline that executes 16 instructions in parallel and runs at 50 MHz. If frequencies scales proportionally, B would still be winning A on more advanced technologies. If frequency doesn't scale proportionally, there would be a point where A wins B.

Once again, thank for all the comments and answers. I wish I could be more precise on my questions.

  • 2
    \$\begingroup\$ No. Your FPGAs can have dedicated macrocells efficiently implementing A but not B or vice versa. \$\endgroup\$
    – Eugene Sh.
    Mar 5, 2020 at 21:06
  • \$\begingroup\$ And what about the case where both A and B don't use macrocells? Can we expect a proportial growth? Or are there other reasons? I know that there are details such as the macrocells you mentioned, but if we abstract such details away, would it be other reasons for not scaling proportionally? \$\endgroup\$ Mar 5, 2020 at 21:13
  • \$\begingroup\$ If you assume both to use primitives only (which is not very realistic) then I think you can expect somewhat proportional result. \$\endgroup\$
    – Eugene Sh.
    Mar 5, 2020 at 21:17
  • \$\begingroup\$ Design speed depends on propagation delays of the lookup tables and the routing. Typically a faster fpga would not only have faster lookup tables, but more routing area. There might be pockets of higher speed but limited by spots of routing congestion. So it is very difficult to estimate without drilling down to the actual details of how a specific design is implemented on a specific fpga. It’s not clearly proportional as it would be with a faster microprocessor. \$\endgroup\$
    – MarkU
    Mar 5, 2020 at 22:39

1 Answer 1


The way FPGAs are synthesised from VHDL through to implementation traverses so many steps, with automated decision making at every step obscuring the details, that it's very difficult to know beforehand for any non-trivial design how it's going to turn out.

If you made a very tightly constrained circuit, say the standard speed test of a large odd number of inverters local to each other connected in a chain, the so-called ring oscillator, then you would expect the 'faster' process to yield a higher frequency oscillator.

However, even that is not certain, for an inverter on a sea-of-gates process might be an inverter, and on another process might be a 32 entry lookup table with one active input and the other four held low. When you implement an architecture that needs (for instance) adders, the lookup table will implement a one bit full adder with the same delay as one inverter, whereas the sea-of-gates might have to build it from lower level gates and all their interconnect.

A usually overlooked difference between processes is the interconnect between active elements. How many levels of hierarchy are there between local cell to cell interconnects, and long lines spanning the chip? If the process includes macro functions like adders, are there fast dedicated local interconnects to build multi-bit adders for little extra delay, or do they need to be connected with general purpose slower routing?

A circuit that uses any clever process features well will usually be faster than a circuit that's not a good fit.

If I want to implement a very speed constrained FPGA design, then the headline speed of the process is a good first start. However, there is so much variation in actual speed as a function of the design fit with the process features that it is worth doing a trial post place-and-route timing for your specific design on other processes.


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