Quartus Signal Tap is extremely beneficial in debugging complex problems. However, there is no such toolset in the Microsemi Libero SmartDebug toolset. I would expect that Microsemi does provide capability to create an internal logic analyzer by using the device resources but don't know how it can be done. Any ideas?
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asked Mar 5, 2020 at 21:41
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Microsemi use Synposys Synplify for the synthesis part. This program can be opened as standalone or can be opened from within Libero by write clicking the synthesis icon (in the Enhanced Tool Flow) and then selecting "open interactively".
Microsemi has also made a deal with Synposys to license their Identify ME. This program makes it possible to implement an embedded logic analyser in Microsemi Flash based devices using its internal logic resources. This is the closest one can get to signal tap II like functionality with Microsemi devices. It is inferior to signal tap II in some ways but also has capabilities that are not found in it.
I could not force Libero to not optimize out certain non-fanout signals I had added to the design to aid in debug. In Quartus we just use the noprune attribute in this case and it works. But in case of Libero, using syn_noprune, syn_preserve or syn_keep does not give the desired result. The registers always get optimized out. The only way is to add them to a watch list using the Identify ME.
The entire design and debug tool suite which includes Libero, Synplify, Identify ME e.t.c is not as elegant in its design and ease of use as Quartus. It has its weaknesses and some occasional strengths over Intel FPGAs and their design and debug tool suite. One must be aware of their overall inferiority when compared with Quartus.
Caution: The SmartDebug ActiveProbe cannot be used at same time as Identify ME. Apparently, the SmartDebug and Identify ME are not able the share the JTAG cable used to communicate with the FPGA. Microsemi has confirmed this.
