# Signal propagation when observing integrated circuits

Consider this image: ... It says "4-digit serial shift register, based on D-type latches" (please correct me if this is not a valid terminology). Clearly, I can't understand a property of D-latch to hold back an input signal for 1 CLK cycle. Is it correct assumption that we should observe signal propagation starting from N-th (4th in this case) latch and going left until 1st one? I mean, if we look from left to right, the register does not really shift, on the first high CLK, it just fills up with all "1"s.
UPDATE: Basically, an essence of my question is - what goes first: D(k)->Q(k), or Q(k-1)->D(k)?

• In my terminology this is definitely NOT a latch (which is IMO always level-activated and hence transparent), this is a register (which is IMO always edge-triggered). Nov 8 '12 at 14:54
• I didn't write it was a latch, I wrote "<...>*based* on D-type latches<...>" Nov 8 '12 at 15:01
• Languages adopt different terms for the same concept. In English we would call the element a D-type flip flop. The Russian seems to be referring to this block as a "trigger" - clearly borrowed and transliterated word, perhaps originally adopted somewhat informally. Nov 8 '12 at 15:22
• Hm, could you please elaborate on an intuition behind words "latch" vs "flip-flop" vs "trigger"? I'm a little confused. Nov 8 '12 at 15:25
• In my terminology a latch is level activated (commonly implemented as one flip-flop style storage element). A register is edge-triggered (commonly implemented as two flip-flop style storage elements, each activated by the opposite polarity of the clock signal - a master-slave arragement). Nov 8 '12 at 16:15

Here is a simplistic explanation:

The D-type latch shown is a positive edge sampling type latch - Note the triangle indication on the clock input. This means it only reads data placed on the D input, at the time when the CLK signal is at its rising edge.

• So at first rising edge of CLK signal, TA samples the value at D, copies it to Q.
• TB, TC and TD at the instant of this edge, do not have any meaningful value, they just read and latch (put on Q) whatever arbitrary value was at their input previously.
• At second rising edge of CLK, TA samples whatever fresh value is at D.
• At the same time, TB samples and latches the value placed on TA's Q pin from previous cycle.
• Values at TC and TD remain arbitrary "meaningless data", ignore them for now.
• At third rising edge, TA samples latest value, TB picks up TA's previous value, and TC picks up TB's previous value.
• Value at TD is still to be ignored as "meaningless data".
• At fourth rising edge, TA samples afresh, TB reads TA's previous, TC reads TB, and TD reads TC.
• At this time, the data that had been asserted on the data input line in the beginning, is showing on the output Q of TD - It has been "shifted" during the four rising edges of the clock, from left to right.
• Outputs of TA, TB, TC and TD are now known, meaningful bits of data.
• At every following rising edge of CLK, the bits keep getting shifted left to right, TA --> TB --> TC --> TD --> out.

That is how the arrangement of latches you have shown, acts as a "shift" register: The values keep shifting left to right once per clock cycle's rising edge.

• So, essentially, it means that the proper case would be Q(k-1)->D(k) (for k!=1) and for the first one DataInput -> D(1)? Nov 8 '12 at 14:02
• Yes, at the instant when the clock signal is at its rising edge. Nov 8 '12 at 14:18

Let
t0 = time right before CLK will go 0 --> 1
t1 = time after CLK went 0 --> 1

Try to look at all D-Flip-Flops at once at t1 and at t0.

Q of any Flip-Flop at t1 will be in the state as D of the same particular Flip-Flop was at t0.

So the solution is NOT to consider the signal propagating one or the other way, but to see it happen all at once (which is actually the case because all FFs are triggered at the same time). The bit pattern of the Qs is shifting from left to right, but the clocking of the FFs is happening at the same moment for all FFs.

• All stages clock at the same time, but the end result is that the signal propogates from left to right with a delay of one clock at each state. Nov 8 '12 at 15:20
• Is the stage one flip-flop? So when a book reads, "...taken from Q at previous stage...", it means Q from a last flip-flop? Nov 8 '12 at 15:28
• @Chris Stratton: if you mean by "signal" the data stored in the FFs I agree. The CLK signal, however, does not propagate from left to right (at least it should not be considered that way), but acts simultaneously on all FFs.
– Curd
Nov 9 '12 at 9:30
• @Владислав Бураков: yes.
– Curd
Nov 9 '12 at 9:31

Indeed, you misunderstand the latches in some way. The signal goes left to right. Q is an output, and D is an input. The latch maintains a state and constantly outputs it on Q. It also ignores input D most of the time. When a clock edge arrives, a latch accepts the value of input D, and adopts it as its new state. Some time later, its output Q will reflect the new state.

Input D must be stable for some minimum time before the clock arrives (called the setup time) as well as afterward (the hold time).

So for the shift register to work, the outputs have to observe the setup and hold times of the inputs. The flip-flop cannot change its output too quickly after clocking the new state; it must continue to hold the previous output for the duration of the required holding time.

The timing is the key; without it, it is impossible to see how the shift register could work properly. If every flip-flop were to abruptly change its output on the clock edge, it would be chaos.

What a flip flop does:

At the positive edge of clock, it puts on Q whatever was on D.

In pseudo code:

if(clock_rising_edge): Q = D


At other times, the value of D is not really important, because it does not affect Q. In a way, D is sampled at the (+) clock edge and transferred into Q.

In the difference equation terminology you are using: $$Q(k) = D(k-1)$$

In the diagram, you have 4 flip flops, and according to the text, they are internally constructed using D-latches, but how exactly they are constructed is not important at this point (there are multiple ways).

So to begin with, each flip flop has its Q at some value (lets say 0, like after a CLR assertion). From the diagram, ABCD = 0000.

At the 1st clock positive edge, each flip-flop will transfer what is in its D input to its Q output. So the output will be ABCD = X000, where 'X' is the input of the leftmost flip-flop at the clock edge. With this logic we can construct the following table:

t  Input  ABCD
0    1    0000
1    1    1000
2    0    1100
3    1    0110
4    x    1011


Where:

• t is sample time, so at every increment there is a positive clock edge.
• Input is the leftmost input.
• ABCD is the collection of the flip-flop outputs, as per the posted diagram.

As a difference equation:

$$A(k) = Input(k-1)$$ $$B(k) = A(k-1)$$ $$C(k) = B(k-1)$$ $$D(k) = C(k-1)$$

As you can see, the input was sequentially 1101 , and this value was shifted into ABCD (in reverse order) in 4 clock cycles. And this the concept of what the diagram describes: a shift register.