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I've just started to read about layout (beginner) and I came across this in Baker's book,

enter image description here

As you can see in the above, the substrate connection is made with a p+ active region. This makes sense for a single NMOS. But what if I had another NMOS right beside this that I wanted to connect a different substrate voltage to (body biasing)? Is there no seperation between the two?

In other words, the substrate connection in the above doesn't seem to be restricted to just this device. What if I wanted to add another device with a different substrate voltage, how would that work since they both now share the p-substrate and hence the first device's substrate voltage? How do you isolate them?

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If you want a different substrate voltage in p-substrate process:

1) Create a n-well in the p-substrate and connect this new n-well to VDD. The depletion layer between the n-well and the p-substrate does the isolation job.
2) Inside the n-well, create a p-well and connect this to the body-bias voltage.
3) Inside the p-well you can create n-mos transistors whose substrate voltage is different from the rest of the chip.

n-mos ---> p-well(VSS2) ---> n-well(VDD) ---> p-substrate(VSS1)

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  • \$\begingroup\$ This is called a "triple well" structure, not all processes have this option! \$\endgroup\$ – Bimpelrekkie Mar 6 at 7:26
  • \$\begingroup\$ @Bimpelrekkie I maybe wrong but I think tsmc has this ready since 180nm process. They call it deep nwell or DNW. Ofcource have to pay extra if you add DNW layers \$\endgroup\$ – across Mar 6 at 7:33
  • \$\begingroup\$ "Triple well" has been in use since the late 1990s, it is nothing new. My point is that you cannot expect every process to have the option. For the "P-well inside the N-well" additional process steps are needed. On the cheapest processes, those steps are not available. Not all designs need the triple-well structure. \$\endgroup\$ – Bimpelrekkie Mar 6 at 7:37
  • \$\begingroup\$ Haha ok not all designs need this but are you sure not all latest tcmc fabs have DNW option if the customer want to? \$\endgroup\$ – across Mar 6 at 7:44
  • \$\begingroup\$ Yes I am sure that not all processes have a DNW option even if the customer wants it. An IC fabrication process is like a recipe. Changes to the recipe can only be made when the complete recipe has been verified. So for a given process having a DNW is either part of the standard process, it might be an option or it is simply not available. If the customer needs DNW then the customer needs to select a process that supports DNW. \$\endgroup\$ – Bimpelrekkie Mar 6 at 7:58
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In most integrated circuit, all the substrates are connected to the same potential. For PMOS, this usually is the higher potential available, and for NMOS, the lowest available. If you want different substrates voltages, you need to use a fabrication technology like Sillicon On Insulator (SOI).

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  • \$\begingroup\$ No, you don't need SOI. Twin well technology has been around for a long time. \$\endgroup\$ – Elliot Alderson Mar 6 at 13:20

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