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As I cannot manage to find it done on internet, I wonder if it is possible to program a CAN controller in a CPLD ? It's look like it is going to require a least an FPGA.

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  • \$\begingroup\$ Sounds like a very expensive way to make a CAN controller... can you share why you'd like to do it this way? \$\endgroup\$ – Martin Thompson Nov 8 '12 at 14:56
  • \$\begingroup\$ There is a very narrow offer in stand-alone CAN controller and I'm looking to replace one that is 5V, parallel driven, to a 3.3V one. But in 3.3V, I find only serial CAN controller (SPI). This will already imply some software rework on the CPLD controlling it. I'm just trying to see all the possibility here. \$\endgroup\$ – jojo l'abricot Nov 8 '12 at 15:15
  • \$\begingroup\$ yes, if you need a standalone parallel controller it could well make sense \$\endgroup\$ – Martin Thompson Nov 9 '12 at 9:24
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There is a CAN Protocol controller on OpenCores. It has a size of 930 flip-flops. You can usually estimate 1 flip-flop per CPLD macrocell. Though as The Photon mentions in his answer to this question:

Finally, though the estimate of 1 flip-flop per macrocell is accurate for classical CPLDs like the one you linked to, some vendors (Altera & Lattice come to mind) have taken a major architectural excursion in their newest CPLD families. These devices are more like mini-FPGAs than like the classical CPLD, and I'm not sure that they calculate their "macrocell-equivalent" sizes according to this formula. The new devices are likely to have more flip-flops per device, but not allow very wide fan-ins to the logic in each cell.

If you filter your search on Digikey to just CPLDs that have greater than 930 macrocells and that are in stock, it returns 168 results, all Altera and Lattice. So, that CAN core should fit in CPLDs of a certain architecture.

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    \$\begingroup\$ Thanks ! Especially the input of the different macrocell size formula, I would have missed that. \$\endgroup\$ – jojo l'abricot Nov 8 '12 at 14:00
  • \$\begingroup\$ Just be aware that with the more FPGA-like "CPLDs" you may not be register limited anymore. As a first approximation, you can treat traditional CPLDs (logic-array+reg) as "logic is free, registers are limited" and FPGA-like (lookup-table+reg) architectures as "logic is limited, registers are free" \$\endgroup\$ – Martin Thompson Nov 9 '12 at 9:23

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