As I cannot manage to find it done on internet, I wonder if it is possible to program a CAN controller in a CPLD ? It's look like it is going to require a least an FPGA.
There is a CAN Protocol controller on OpenCores. It has a size of 930 flip-flops. You can usually estimate 1 flip-flop per CPLD macrocell. Though as The Photon mentions in his answer to this question:
Finally, though the estimate of 1 flip-flop per macrocell is accurate for classical CPLDs like the one you linked to, some vendors (Altera & Lattice come to mind) have taken a major architectural excursion in their newest CPLD families. These devices are more like mini-FPGAs than like the classical CPLD, and I'm not sure that they calculate their "macrocell-equivalent" sizes according to this formula. The new devices are likely to have more flip-flops per device, but not allow very wide fan-ins to the logic in each cell.
If you filter your search on Digikey to just CPLDs that have greater than 930 macrocells and that are in stock, it returns 168 results, all Altera and Lattice. So, that CAN core should fit in CPLDs of a certain architecture.