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I have been reading about DDR lately and I am not able to understand the exact use of the DQS signal. The timing diagrams show dqs in phase with clock so why cant the clock only be used for the write and read, how does dqs improve performance of ddr.

Read Timing Diagram

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DQS is aligned with the data bus DQ, not the clock. It is used to precisely time where the DQ data are to be sampled. It’s a necessary complexity in order to support the clock speeds contemporary DDRx DRAM can achieve, in a way that supports a large number of chips and groups-of-chips (that is, ranks.)

DQS and DQ do have a rough alignment with the input clock, but this relationship isn’t tightly defined - certainly not well enough to achieve the timing accuracy needed to capture DQ correctly.

Instead, DQS and DQ are source-synchronous: they travel together from host to DRAM and vice-versa, and so have the same point-to-point delay. This applies in both directions: on writes the host drives DQ and DQS; on reads the DRAM chip drives them.

And it gets even more complicated. On writes, the host sends DQS phase shifted by 90 degrees and the DRAM catches DQ in the middle of its validity window. On reads, the DRAM sends DQS aligned with DQ, and the host phase-shifts DQS internally using a Delay Locked Loop (DLL) and captures DQ with that internal clock. In both cases the goal is the same: to get the best possible timing margin on DQ.

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  • \$\begingroup\$ can u please provide an example how source synchronous is better than a global clock. \$\endgroup\$
    – Yohan0022
    Mar 6, 2020 at 6:37
  • \$\begingroup\$ Source-sync is a key technique used in many high-speed interfaces. DDR DRAM is one example; RGMII is another. The key benefit is that source-sync controls skew between data and clock as they are sent together from one place to another. It breaks a dependency on turn -around from system clock through peripheral then back. \$\endgroup\$ Mar 6, 2020 at 6:42
  • \$\begingroup\$ Another reason is that DQS has precisely the same loading as the DQ signals (a single load), unlike the clock which may have multiple loads which can cause skew. \$\endgroup\$ Mar 6, 2020 at 12:47
  • \$\begingroup\$ Not just loading per se, but trace length. Large DRAM systems have significant transmission line delay that needs to be accounted for in the system timing model. This delay would be practically impossible to reliably characterize and compensate for without using a known timing reference. DQS provides that reference as a signal that ‘flies with’ DQ, with a known set of edges that the receiver uses to capture DQ. \$\endgroup\$ Mar 6, 2020 at 17:50

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