I'm interested in increasing the transmission rate over Cat5 for a personal project. (Cat5/5e/6 will be chosen because of it's properties and obtainability but will not be used in the standard way)

In any case what I'm interested in using a "multi-level bits" per clock of transmission. Digital communication almost always uses a single bit per clock.

For example, using a single bit(0 or V) in cat5 at 100MHz allows only for a 100Mbits data rate. Using 4 bits allows for and effective rate of 400Mbits/TP(or over Cat6a, 2GB/TP). For my project this is significant.

Obviously adding more bits per clock increases complexity and decreases the noise immunity but I feel that it could be done with a few logic gates and will work for my particular application.

Since the signals will be differential it seems it may be pretty easy on the tx side by actually not having one of the lines being the mirror images but independent. Noise immunity will still be retained due to the differential nature.

Essentially on each end of the line we will have 4-bit DAC(for tx) and ADC(for rx) to convert to and from the multi-level representation.

My question is, besides the added cost and complexity(which doesn't seem to be all that great?), are there any other reasons why it is bad.

I conclude that there seems to be no loss of noise immunity:

  1. Asymmetric differential signaling is used. External noise will be canceled out in exactly the same manner when symmetric different signaling is used(assuming that the noise does not depend on the voltage in the wire)

  2. The noise margins can be kept the same by simply amplifying and attenuating the signal before and after transmission. e.g., normally 0-3.3v are used. We can amplify this to 0-26.4V which will give the same distance between each level(3.3V). Of course, the cost is 8 times the transmission power but this would probably be similar to when using a single-bit/clock rate that is 8 times larger.

Therefor, best I can decern, the real cost in achieving around an order of magnitude in throughput is a few dollars in parts. (a monolithic tx and rx ic would reduce the complexity to near 0).

Is there any real downside besides what I have listed. Basically what are the practical drawbacks?

  • \$\begingroup\$ What is the maximum length of the cable? \$\endgroup\$ – apalopohapa Nov 8 '12 at 19:15
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    \$\begingroup\$ "Digital communication almost always uses a single bit per clock." Umm... not since a couple of decades ago. Several other "leaps" in the question, perhaps a bit of net searching before revisiting this? \$\endgroup\$ – Anindo Ghosh Nov 8 '12 at 19:16
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    \$\begingroup\$ @JonSlaughter you're wrong. Ethernet, as described on Wikipedia: "1000BASE-T uses all four cable pairs for simultaneous transmission in both directions through the use of adaptive equalization and a 5-level pulse amplitude modulation (PAM-5) technique. The symbol rate is identical to that of 100BASE-TX (125 Mbaud) and the noise immunity of the 5-level signaling is also identical to that of the 3-level signaling in 100BASE-TX, since 1000BASE-T uses 4-dimensional trellis coded modulation (TCM) to achieve a 6 dB coding gain across the 4 pairs." \$\endgroup\$ – Jim Paris Nov 8 '12 at 19:27
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    \$\begingroup\$ @JonSlaughter Quadrature Phase Shift Keying was introduced for commodity consumer data modems used over dial-up phone lines, in the 1980s. 1 bit per clock was never the same again. \$\endgroup\$ – Anindo Ghosh Nov 8 '12 at 19:34
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    \$\begingroup\$ I've deleted some conversational and sometimes inflammatory comments. Please use this space to help others understand the question, and be polite to each other. \$\endgroup\$ – clabacchio Nov 9 '12 at 18:17

There are some good reasons not to do what you imagine.

First, the signal level at your receiver will vary quite a bit depending on the properties and length of your cable (and if you are out of luck, also on the phase of the moon). You will have to calibrate your receiver for the particular cable.

Reflections of large signals (0->1111 transition) might swamp small signals (0->0001 transition).

A 4-bit (=16 level) flash AD at 100 Mhz is not trivial.

Generally, doubling the baudrate is often much easier than doubling the number of levels that have to be resolved.

  • \$\begingroup\$ Given that you can get "16" bit > 100 MSPS ADCs, finding a device which can give you four real bits should not be a problem. The 8-bit parts used in various DIY oscilloscope projects might be more relevant. \$\endgroup\$ – Chris Stratton Nov 8 '12 at 19:18
  • \$\begingroup\$ Yes, but there is a limitation in this doubling. Analogous to doubling the cpu frequencies... there comes a point when it just can't be done any more and some alternate direction must be taken. Relfections may or may not be an issue depending on length and termination quality. It may be the real down side but I guess real experimental proof is needed. \$\endgroup\$ – JonSlaughter Nov 8 '12 at 19:26

There is a fundamental flaw in your logic, which is that you are assuming there is no such thing as differential mode noise. There certainly is! Even if no differential noise is added, some amount of common mode noise will appear as differential noise at the receiver.

Part of your basic idea is correct though, which is that the total data rate is governed both by the bandwidth and the signal to noise ratio. Look up Shannon and Nyquist, and you should find the formal mathematical description of what the maximum possible data rate is for a given bandwidth and S/N ratio.

So to answer your question, yes there is a downside to what you are proposing. The more levels you use, the lower the noise immunity, which then effectively lowers the data rate. Multi-level signalling makes sense in cases where the bandwidth has to be limited and sufficient signal to noise ratio is available. However for ordinary cables, that is not the case. This is why most protocols take the easier route to getting the maximum data rate by cranking up the bit rate to where two signal levels is just what the remaining signal to noise ratio can support.

  • \$\begingroup\$ Olin, the differential noise will exist on normal single bit methods. The larger voltage transitions may increase differential noise, maybe to an unacceptable level BUT this is why I'm asking questions. Every method has it's drawbacks. I do not think differential mode noise is one of them in this specific case but it is possible. \$\endgroup\$ – JonSlaughter Nov 8 '12 at 20:59
  • \$\begingroup\$ @JonS: There are lots of ways differential mode noise can show up at the receiver. Assuming all noise is external and common mode is not good since that's simply not how real systems work. Much of the external noise will be common mode, but some not, and even some of the common mode noise will appear as differential noise at the receiver. You are going to have differential noise. There will be a finite signal to noise ratio, and that together with the bandwidth will limit the total data transfer rate. You can't cheat basic physics. \$\endgroup\$ – Olin Lathrop Nov 8 '12 at 21:08
  • \$\begingroup\$ I can't argue with you on the subject. Obviously there is an effect but the issue is how much. Since ethernet does not seriously suffer from these issues AFAIK, it seems to me like it is not a big deal. I must assume that for Cat5+ the issue is not a problem(in general). The question then remains if the multiple voltages per conductor increase this problem. I do not know and you have no proved this in any way(no offense, just that you haven't given any logic or evidence to suggest it will be an issue when going from single to multiple voltage levels). \$\endgroup\$ – JonSlaughter Nov 8 '12 at 21:12
  • \$\begingroup\$ Basically you are stating theoretical facts. It is obvious that adding multiple voltage levels per conductor will decrease the noise immunity, which is why I suggested pre-amplifying them to a larger voltage level to keep the same interlevel voltage margins. So, again, the question is not if but how much and that takes either a lot of math or real world data... \$\endgroup\$ – JonSlaughter Nov 8 '12 at 21:14

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