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I have been trying to understand that what is the added benefit in shrinking components such as DSP slice, IPU, LCD controller etc into SoC instead of keeping them separate.

  • Is this done only to decrease the area footprint of the device?
  • Is there an added benefit in terms of latency?
  • Is cpu more optimized to talk to components within the SoC?
  • If cpu is optimized what kind of optimization is used?
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  • \$\begingroup\$ Size, cost, and sometimes performance. \$\endgroup\$
    – Mattman944
    Mar 7 '20 at 23:22
  • \$\begingroup\$ yes I am looking more onto what kind of optimization is done to boost performance other then the fact that being in close proximity the signal travels faster. \$\endgroup\$ Mar 8 '20 at 12:12
  • \$\begingroup\$ Sometimes architecture compromises are made due to pin count limitations when circuits are in separate ICs. So, optimization could be removing the compromises. \$\endgroup\$
    – Mattman944
    Mar 8 '20 at 12:22
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Is this done only to decrease the area footprint of the device?

That can be one reason, and it's especially important to highly integrated devices. Think smartphones. No way they could be this small if all the functionality was spread out across multiple packages.

Also, less different things to solder onto a board means less sources of error, once you've gotten your high-pad-count process to work reliably.

Also, less assembly steps typically means "cheaper" in the end product, and that's an important factor basically anywhere.

Also, if everything that's complicated to talk to, layout high-speed traces for, design power architecture for etc is in one chip, you're offloading the design effort from the device manufacturers to the SoC designers, which typically means that the people designing the devices can work with less skills, and/or lower design and testing effort. Another big plus! Many things simply couldn't be built, otherwise, since there's simply not enough skilled engineers in this world.

  • Is there an added benefit in terms of latency?
  • Is cpu more optimized to talk to components within the SoC?
  • If cpu is optimized what kind of optimization is used?

There might be, but this really depends on what you're looking at, and no sensible general answer can be given. The only thing that's relatively general is that the shorter the connections, the easier it is to make them work for high frequency (but that comes at high costs – doing stuff on silicon isn't cheap or easy, and achieving RF isolation within a chip is harder than spread out).

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  • \$\begingroup\$ Allright so the argument mainly is saving area footprint. My concern is that is there any proprietary optimization? say if the SoC has both CPU and GPU, so dealing with such SoC is similar to dealing with a device that has CPU and GPU as separate components? or if GPU is integrated with CPU in SoC they perform as a single unit as the code for using the SoC is optimized to automatically to offload the task to both of them appropriately. That what I meant when I said optimization in my question. \$\endgroup\$ Mar 8 '20 at 12:10
  • \$\begingroup\$ no, it's not "mainly", but that's one common thing. \$\endgroup\$ Mar 8 '20 at 12:30
  • \$\begingroup\$ and what kind of optimization is done in a GPU/CPU bundle within a SoC is, as I wrote, dependent on the choices made by the designers of that SoC and no general answer can be given. \$\endgroup\$ Mar 8 '20 at 12:31

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